o-digital converter with an
on-chip, high performance sample-and-hold amplifier. The
HMXADC9225 uses a multistage differential pipelined
architecture with output error correction logic to provide 12-bit
accuracy at 20 MSPS data rates, and guarantees no missing
codes over the full operating temperature range.

The HMXADC9225 combines a radiation hardened SOI-IV
Silicon On Insulator (SOI) process and very low power
consumption.

The input of the HMXADC9225 allows for easy interfacing to
space and military imaging, sensor, and communications
systems.

With a truly differential input structure, the user can
select a variety of input ranges and offsets including
single-ended applications. The dynamic performance
is excellent.

The sample-and-hold amplifier (SHA) is well suited for
both multiplexed systems that switch full-scale voltage
levels in successive channels and sampling single-
channel inputs at frequencies up to and well beyond
the Nyquist rate.

A single clock input is used to control all internal
conversion cycles. The digital output data is presented
in straight binary output format.

FEATURES
Output Enable (OE)
The OE input allows user to put the
digital outputs into a high impedance
tri-state mode.

Dual Power Supply Capability
The HMXADC9225 uses a single +5
V power supply simplifying system
power supply design. It also features
a separate digital driven supply line to
accommodate 3 V and 5 V logic
families.

On-Board Sample-and-Hold (SHA)
The versatile SHA input can be
configured for either single-ended or
differential inputs.


Mixed Signal Rad Hard Process
The HMXADC9225 is fabricated on
space qualified SOI CMOS process.
High-speed precision analog circuits
are now combined with high-density
logic circuits that can reliably
withstand the harshest environments.

Space Qualified Package
The HMXADC9225 is packaged in a
28 lead ceramic flat pack.

Low Power
The HMXADC9225 at 240 mW
consumes a fraction of the power of
presently available in existing
monolithic solutions.





Monolithic 12-Bit, 20 MSPS A/D
Converter

Rad Hard: >1000 krad Total Dose

Low Power Dissipation: 240 mW

Single +5 V Analog Supply

5V or 3.3V Digital and I/O Supply

No Missing Codes Guaranteed

Differential Nonlinearity Error: 0.4
LSB

Complete On-Chip S/H Amplifier

Signal-to-Noise and Distortion
Ratio: 69.6 dB

Spurious-Free Dynamic Range:
81 dB

Straight Binary Output Data

28-Lead Ceramic Flat Pack


HMXADC9225
Advanced Information



BLOCK DIAGRAM

5
3
3
4
A/D
A/D
A/D
A/D
MDAC1
X16
MDAC2
X4
MDAC3
X4
Diff
Buffer
Master Bias
Clock
Gen
CML
Gen
Correct
Logic

Data
Output
Drivers


Output
Tri-State
Control
S/H
RBIAS
CML
Clock
External
Reference
Input
Output
Enable
VINP
VINN
AVDD
AVSS
DRVDD
D0 D11
IREF
REFP, REFN
Cext
DRVSS
VREF
REFCOM
REFN
REFP
5k


PIN DESCRIPTION

Pin
Pin Name
Description
1
CLK
Clock Input
2
BIT 12
Least Significant Data Bit (LSB)
3-12
BIT 11 2
Data Output Bit
13
BIT 1
Most Significant Bit (MSB)
14
OE
Output Enable (high active)
15
AVDD
+5V Analog Supply
16 AVSS
Analog
Ground
17
RBIAS
Reference Current Bias Resistor
18
VREF INPUT Reference Voltage Input
19 REFCOMM
Reference
Common
20
CAPB
Noise Reduction Pin
21
CAPT
Noise Reduction Pin
22
CML
Common Mode Level
23 VINA
Analog
Input
(+)
24 VINB
Analog
Input
(-)
25 AVSS
Analog
Ground
26
AVDD
+5V Analog Supply
27
DRVSS
Digital Output Driver Ground
28
DRDVDD
+5V or 3.3V Digital Output Driver Supply

CLK
BIT 12 (LSB)

BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT5
BIT 4
BIT 3
BIT 2
BIT 1 (MSB)

DRVDD
DRVSS
AVDD
AVSS
VIN A
VIN B
CML
CAPT
CAPB
REFCOM
VREF IN
RBIAS
AVSS
AVDD
OE
1
28
2
10
3
11
4
12
5
13
6
7
8
9
14
27
19
26
18
25
17
24
16
23
22
21
20
15

SIGNAL DEFINITION

DRVDD

The DRVDD power supply can be either 5.0V or
3.3V. The voltage used will also define the voltage
level of all of the following digital I/O signals including
Clock, Output Enable, all data output signals.


OUTPUT ENABLE (OE)

This signal will control the digital output signals. A
high logic level will enable the outputs and a low logic
level will put the outputs into a high impedance state.

2 www.honeywell.com. HMXADC9225
Advanced Information



TIMING DIAGRAM

t
CL
t
CH
t
CD
S1
Data 1
S2
S3
S4
Analog
Input
Clock
Data
Out
t
C



RADIATION PERFORMANCE

Total Ionizing Radiation Dose

The HMXADC9225 will meet all stated functional
and electrical specifications over the entire
operating temperature range after the specified
total ionizing radiation dose. All electrical and
timing performance parameters will remain within
specifications after rebound at VDD = 5.0 V and
T =125
°C extrapolated to ten years of operation.
Total dose hardness is assured by wafer level
testing of process monitor transistors using 10
KeV X-ray and Co60 radiation sources.
Transistor gate threshold shift correlations have
been made between 10 KeV X-rays applied at a
dose rate of 1x10
5
rad(SiO
2
)/min at T = 25
°C and
gamma rays (Cobalt 60 source) to ensure that
wafer level X-ray testing is consistent with
standard military radiation test environments.

Transient Pulse Ionizing Radiation

The HMXADC9225 is capable of writing, reading,
and retaining stored data during and after
exposure to a transient ionizing radiation pulse,
up to the specified transient dose rate upset
specification, when applied under recommended
operating conditions. To ensure validity of all
specified performance parameters before, during,
and after radiation (timing degradation during
transient pulse radiation is
±10%), it is suggested
that stiffening capacitance be placed near the
package VDD and VSS. If there are no operate
through or valid stored data requirements, typical
circuit board mounted de-coupling capacitors are
recommended.

The HMXADC9225 will meet any functional or
electrical specification after exposure to a
radiation pulse up to the transient

dose rate
survivability specification, when applied under
recommended operating conditions. Note that the
current conducted during the pulse by the ADC
inputs, outputs, and power supply may
significantly exceed the normal operating levels.
The application design must accommodate these
effects.

Neutron Radiation

The HMXADC9225 will meet any functional or
timing specification after exposure to the
specified neutron fluence under recommended
operating or storage conditions. This assumes
equivalent neutron energy of 1 MeV.

Soft Error Rate

The HMXADC9225 is capable of meeting the
specified Soft Error Rate (SER), under
recommended operating conditions. This
hardness level is defined by the Adams 90%
worst case cosmic ray environment for
geosynchronous orbits.

Latchup

The HMXADC9225 will not latch up due to any of
the above radiation exposure conditions when
applied under recommended operating
conditions. Fabrication with the SIMOX substrate
material provides oxide isolation between
adjacent PMOS and NMOS transistors and
eliminates any potential SCR latchup structures.
Sufficient transistor body tie connections to the p-
and n-channel substrates are made to ensure no
source/drain snapback occurs.

3 www.honeywell.com. HMXADC9225
Advanced Information




RADIATION SPECIFICATIONS
(T
MIN
to T
MAX
with AVDD = +5V, DRVDD = +5V, C
L
= 20 pF)

Parameters
Min
Max
Units
Total Dose Hardness
>1 x 10
6

Rad
(SiO
2
)
Dose Rate Upset Hardness
TBD

Rad(Si)/sec
Dose Rate Survivability
TBD

Rad(Si)/sec
Soft Error Rate

TBD
Errors/bit/day
Nuetron Fluence Hardness
TBD

/cm
2




Absolute Maximum Ratings


(AVDD = +5V, DRVDD = +5V, unless otherwise noted)

Parameters
Min
Max
Units
AVDD
5.5
V
DRVDD
5.5
V
AVSS -0.3

V
REFCOMM -0.3

V
CLK
5.5
V
Digital Outputs

5.5
V
VINA, VINB

5.5
V
VREF
5.5
V
CAPB, CAPT

5.5
V
Junction Temperature

+175
o
C
Operating Temperature
-55
+125
o
C

Recommended Operating Conditions


Parameter
Min
Typical
Max
Units
AVDD (Supply Voltage)
4.5
5.0
5.5
V
DRVDD (Supply Voltage, 5.0V)
4.5
5.0
5.5
V
DRVDD (Supply Voltage, 3.3V)
3.0
3.3
3.6
V
TA (Ambient Temperature)
-55
25
125
°C
Vpin (Voltage on any pin referenced to VSS)
-0.3

VDD+0.3
V

ESD (Electrostatic Discharge) Sensitive

The HMXADC9225 is sensitive to ESD above levels
of 2000 volts. Proper ESD precautions should be
taken to avoid degradation or damage to the device.
4 www.honeywell.com. HMXADC9225
Advanced Information



DC SPECIFICATIONS

(AVDD = +5V, DRVDD = +5V, f
SAMPLE
= 20 MSPS, VREF 2.0V, VINB = 2.5V dc, T
MIN
to T
MAX
unless otherwise noted)
Parameter
Min
Typical
Max
Units
RESOLUTION 12


Bits
MAX CONVERSION RATE
20


MHz
INPUT REFERRED NOISE





VREF = 2.0V

0.17

LSB rms





ACCURACY




Integral Nonlinearity (INL)

±1.2
LSB
Differential
Nonlinearity
(DNL)

±0.4
LSB

No Missing Codes

12

Bits Guaranteed

Zero Error (@ +25
°C)

±0.3
%
FSR

Gain Error (@ +25
°C)
1


±0.5
%
FSR

Gain Error (@ +25
°C)
2


±0.4
%
FSR





Temperature Drift