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design ideas
Many process-control sensors,
such as thermistors and strain-
gauge bridges, require accurate bias cur-
rents. By adding a single current-set-
ting resistor, R
1
, you can configure volt-
age-reference circuit IC
1
to produce a
constant and accurate current source
(Figure 1). However, the sources
errors depend on the accuracy of both
R
1
and IC
1
and affect measurement
accuracy and resolution. Although you
can specify high-precision resistors
whose accuracy exceeds that of most
commonly available voltage-reference
ICs, the voltage references error dom-
inates this current sources accuracy.
Although the manufacturer mini-
mizes the voltage references tempera-
ture sensitivity and output-voltage
error, sensitivity to power-supply vari-
ations can affect its accuracy, especial-
ly in process-control applications that
must operate over a wide range of sup-
ply voltages.
A cascode-connected pair of JFETs,
Q
1
and Q
2
, form a constant-current
source that minimizes the reference
circuits sensitivity to supply-voltage
fluctuations and extends IC
1
s operat-
ing voltage beyond its 5.5V maximum
rating. In addition, Q
1
and Q
2
effec-
tively increase the current sources
equivalent resistance from a few
megohms almost into the gigohm
range. In the circuits Norton model,
equivalent resistance represents the
parallel resistance across an ideal cur-
rent source.
An N-channel JFET operates as a
depletion-mode device at its maxi-
mum saturated drain current when its
gate-to-source bias voltage is 0V. In
contrast to a depletion-mode MOS-
FET that requires a gate-bias voltage
to conduct, the JFET operates in a
default on-state and requires gate-bias
voltage to cut off conduction. As its
gate-to-source voltage becomes more
negative with respect to the source, a
JFETs drain current goes to zero at the
pinch-off voltage. The JFETs drain
current varies approximately with its
gate bias: I
D
I
DSS
(1 V
GS
/V
P
)
2
,
where I
D
is drain current, I
DSS
is the sat-
READERS SOLVE DESIGN PROBLEMS
EDITED BY BRAD THOMPSON
AND FRAN GRANVILLE
design
ideas
MAY 11, 2006 | EDN 75
JFET cascode boosts
current-source performance
Clayton B Grantham, Tucson, AZ
D I s I n s i d e
76
Microcontroller delivers
voltage-multiplied dc power
80
Low-dropout linear regulators
deliver constant currents


What are your design problems
and solutions? Publish them here
and receive $150! Send your
Design Ideas to edndesignideas@
reedbusiness.com.
Figure 1
A pair of cascode-connected JFETs reduces the
effects of power-supply-voltage fluctuations on a current
sources accuracy.
POWER
SOURCE
POWER
RETURN
Q
1
Q
2
V
IN
V
REF
EN
GND
IC
1
LM4132-1.8V
C
1
0.1 F
D
D
S
S
G
G
MMBF4393
I
SOURCE
= (V
REF
/R
1
)
I
GND
.

I
GND
R
1
1k
0.1%
25 PPM/ C
R
2
SENSOR
OR LOAD
REQUIRING
CONSTANT-
CURRENT
DRIVE
POWER-
SUPPLY
INPUT
3
1.5
1
2
2.5
3
3.5
4
9
15
21
27
33
39
POWER-SUPPLY VOLTAGE (V)
CURRENT-
SOURCE
OUTPUT
(mA)
R
1
=510
R
1
=750
R
1
=1k
Figure 2
Setting R
1
to values of 1 k , 750 , and 510
delivers output currents of approximately 1.8, 2.5, and 3.6
mA that are insensitive to a wide range of power-supply
voltages. design
ideas
76 EDN | MAY 11, 2006
The combination of an exter-
nal circuit and a low-voltage
microcontroller occasionally requires
a significantly higher power-supply
voltage. You can use either an exter-
nal boost converter to increase the
logic supply or a buck converter to
decrease an even higher voltage.
However, you can alternatively use
the microcontroller to create a high-
er voltage. For example, some of Cy-
press Semiconductors (www.cypress.
com) PSOC (programmable-system-
on-chip) microcontrollers include a
configurable comparator block that,
with a PWM block, can form the
heart of a simple inductor-based boost
converter (Figure 1). A few external
components implement a 40V power
supply (Figure 2). When the feedback
voltage you apply to Pin 3 (P0.3)
exceeds the comparators software-
defined threshold voltage, the com-
parator shuts off the PWM stage.
When the voltage drops below the
threshold, the comparator re-enables
the PWM block and thus regulates
the output voltage. The voltage reg-
ulator uses only hardware blocks and
V
CC
P0.6
P0.7
P0.5
P0.3
P0.1
P2.7
P2.5
P2.3
P2.1
SMP
P1.7
P1.5
P1.3
P1.1
GND
P0.4
P0.2
P0.0
P2.6
P2.4
P2.2
P2.0
XR
ES
P1.6
P1.4
P1.2
P1.0 15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
5V
INPUT
IC
1
CY8C27443
R
1
1k
400 kHz
R
2
7.3k
R
3
1k
D
1
SCHOTTKY
DIODE
Q
1
IRFD110
L
1
22 H
C
1
10 F
D
S
G
5V
+
40V
OUTPUT
Microcontroller delivers
voltage-multiplied dc power
Aaron Lager, Masterwork Electronics, Santa Rosa, CA
Figure 1
Use a pair of a PSOC microprocessors internal blocks and a few
external components to build a voltage-boost converter. Use a Schottky
diode rated for a peak-inverse voltage of 100V for D
1
. The PSOCs remaining
pins are available for application support.
urated drain current, V
GS
is the gate-to-
source voltage, and V
P
is the pinch-off
voltage.
Assume that IC
1
s output voltage,
V
REF
, remains constant at 1.8V. Be-
cause the output voltage drives Q
2
s
gate, IC
1
s input voltage, V
IN
, equals
V
REF
V
GS(Q2)
, or 1.8V ( 1.2V) 3V.
Thus, Q
2
s gate-to-source voltage rests
at its nominal pinch-off voltage of
1.2V and varies in step with small
changes in current source. As the
power-supply voltage varies from 3V to
more than 30V, then the input voltage
remains almost constant, as you would
expect, because V
REF
also remains con-
stant. The cascoded-FET configuration
increases the current sources Norton
equivalent resistance beyond that of
the voltage reference and R
1
alone. You
can use a single JFET, but stacking two
JFETs further enhances the circuits
effective impedance. Note that IC
1
doesnt degrade accuracy because the
JFETs hold IC
1
s input voltage virtual-
ly constant, and IC
1
effectively cancels
initial gate-to-source-voltage varia-
tions and temperature effects that Q
1
and Q
2
introduce.
Negative feedback in the Kirchhoff-
voltage loop that comprises V
IN
, V
REF
,
and V
GS(Q2)
allows the drain current to
reach an equilibrium bias point that sat-
isfies Q
2
s transfer equation. Compris-
ing the sum of (V
REF
/R
1
) plus IC
1
s
internal housekeeping current, I
GND
,
Q
2
s drain current remains constant.
Adding Q
1
reduces the effects of Q
2
s
output impedance to insignificance.
Adjusting the value of R
1
varies the cir-
cuits output current over a useful range
of 200 A to 5 mA, with Q
2
s saturat-
ed-drain-current specification imposing
an upper limit. If you select a JFET with
higher saturated drain current, make
sure not to exceed Q
1
s maximum
power dissipation.
Note that the circuits lower power-
supply-voltage limit must exceed the cir-
cuits compliance voltage, 3V, plus the
voltage drop that the sensor introduces:
I
SOURCE
R
2
. The circuits upper power-
supply voltage must not exceed
I
SOURCE
R
2
30V. For example, supply-
ing a current of 2.5 mA to a 1-k
pres-
sure-sensor bridge, R
2
, limits the power-
supply-voltage range to 5.5 to 32.5V.
The circuits output current varies less
than 1 A over a wide range of power-
supply voltages (Figure 2).
EDN design
ideas
78 EDN | MAY 11, 2006
thus is immune to the effects of other
activities taking place in the PSOCs
CPU.
However, some microcontrollers
lack a built-in comparator. For these
devices, the Villard Cascade circuit
offers a less expensive alternative to an
external boost-voltage converter (Ref-
erence 1). Most engineers who are
familiar with the Villard Cascade
associate it with high-voltage appli-
cations and do not envision it as a low-
voltage dc-supply technique. The cir-
cuit in Figure 3 requires an ac input
source that you can easily simulate
using a PSOCs internal PWM and
inverter blocks. A square-wave output
voltage appears on Pin 1, and an
inverted version of the same square
wave appears on Pin 2. The voltage
difference between the two pins ap-
plies an ac square-wave voltage to the
cascade.
Figure 4 shows how to configure a
PSOCs internal blocks to drive the
circuit in Figure 3. The PSOCs out-
put multiplexer inverts the PWMs
output and drives Port_0_5, and
Port_0_6 receives the PWMs nonin-
verted output signal. Again, the
PSOC uses hardware blocks to drive
a Villard Cascade voltage multiplier,
and the circuit produces an output
voltage without regard to CPU activ-
ity. For an input voltage, V
IN
, a Villard
Cascade of N stages delivers an output
voltage of V
IN
2N. One stage com-
prises two diodes and two capacitors
(Figure 5). However, the series-con-
nected capacitors and diodes intro-
duce voltage drops that limit the out-
put current available from a Villard
Cascade. In addition, the following
equation imp