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Analysis of Jitter due to Power-Supply Noise in Phase-Locked Loops
Abstract- Phase-locked loops (PLL) in RF and mixed signal VLSI
circuits experience supply noise which translates to a timing jitter.
In this paper an analysis of the timing jitter due to the noise on the
power supply rails is presented. Stochastic models of the power
supply noise in VLSI circuits for different values of on-chip decou-
pling capacitances are presented rst. This is followed by calcula-
tion of the phase noise of the voltage-controlled oscillator (VCO) in
terms of the statistical properties of supply noise. Finally the timing
jitter of PLL is predicted in response to the VCO phase noise. A
PLL circuit has been designed in 0.35
µ
CMOS process, and our
mathematical model was applied to determine the timing jitter.
Experimental results prove the accuracy of the predicted model.
I. I
NTRODUCTION
PLLs are ubiquitous in RF and mixed signal circuits. They are uti-
lized as on-chip clock frequency generators to synthesize the higher
internal frequency from the external lower frequency. In data com-
munications and disk drive read channels PLL, systems are also
used as clock recovery systems. In all of the above applications, the
random temporal variation of the phase, or jitter, is a critical perfor-
mance parameter. Excessively large jitter consumes some of the
clock budget and it can cause error propagation as well as intercom-
munication errors between chips. The PLL circuit operates from the
same supply busses that provide the required voltage to other build-
ing blocks of the chip, thus it is subject to supply noise.
The power supply noise is the switching noise on the power sup-
ply line which consists of the resistive IR drop due to wire resis-
tances and inductive
-noise due to the chip-package wire
inductance. In todays deep submicron design with smaller feature
size, faster switching speeds, the on-chip inductance is also becom-
ing signicant inductive component. There have been several works
on power-supply noise analysis[1],[2],[3],[4]. The power supply
noise may drive the VCO of the PLL away from its correct fre-
quency, causing the unwanted random uncertainty in frequency. In
the meantime, the supply noise affects the performance of the phase
detector and the loop lter (cf. Fig. 1.). In most clock synthesis
applications, a VCO is locked to a very low jitter reference input
signal generated by a crystal. With a careful design of PLL building
blocks, the noise contribution of phase detector, the frequency
divider, and the loop lter can be reduced to a tolerable level. The
dominant noise is thus the phase noise of the VCO. Recently there
have been some works on characterizing the phase noise in electri-
cal oscillators [5], [6]. Paper [7] attempts to analyze the timing jitter
of oscillators due to the power supply and substrate noise. The
oscillator subject to supply noise is considered as a VCO with dif-
ferent control voltages and therefore the jitter effect is viewed as
frequency-modulated sinusoidal waveform. This paper, however,
suffers from one drawback. The VCO system is treated as a deter-
ministic system in the presence of noise.
The goal of the present paper is to predict the timing jitter of a
PLL using a more accurate model for the phase-lock loop in terms
of the jitter in the VCO resulting from the power supply noise. We
focus on the charge-pump PLL due to its widespread application in
todays frequency synthesizers and clock generators for micropro-
cessors. Section II briey explains the block diagram of the PLL
system in the presence of all the relevant noise sources. Section III
gives a statistical modeling of the power supply noise. Section IV
relates the VCO noise to the power supply statistical properties.
Then section V formulates the effect VCO noise source on the out-
put phase of the PLL. In section VI the PLL jitter analysis applies
on a PLL circuit. Finally section VII concludes our analysis.
II. S
YSTEM MODELING FOR PLL NOISE ANALYSIS
The functional block for a phase-lock loop along with various ran-
dom noise sources is shown in Fig. 1. In general all the loop com-
ponents may contribute to the output noise and accumulated jitter.
The effect of noise on the phase detector performance has been
studied in [8] and in any case phase detectors are not a major source
of noise in a PLL. The passive low pass lter introduces thermal
and shot noise. The timing jitter due to these device noise sources
turns out to be signicantly less than that due to substrate and sup-
ply noises [7]. As a result, timing jitter is mainly associated with
two important noise sources:
- noise at the input,
- phase noise of the VCO.
The loop frequency bandwidth of the system determines which
noise source has more impact on the timing jitter of the output. A
narrow loop-bandwidth reduces the impact of the phase noise at the
input on the jitter. Previously more attention has been paid to under-
standing the effect of the input noise source compared to the VCO
phase noise. Furthermore for both clock synthesizers and high per-
formance clock recovery systems an accurate analysis of the output
jitter due to the internal VCO phase noise is important. In this
paper, we focus on the VCO phase noise injection into the PLL
closed loop system.
Lets consider the general case of a PLL shown in Fig. 1. with the
nth-order low-pass lter (LPF) in place, the differential equation
relating the synthesized excess phase and the input phase is as fol-
lows:
(1)
where
is the closed-loop phase error,
is the input reference
phase, G is the closed loop gain constant,
represents the
phase detector function,
is the phase noise source of the VCO.
III. P
OWER SUPPLY NOISE ANALYSIS
A power supply distribution model must include the chip-package-
interface power distribution model, the on-chip power bus model,
I This research was funded in part by SRC under contract no. 98-DJ-606.
K
D
f
PD
(.)
Phase Detector
L
(n)
[v
LP
] = L
(m)
[v
PD
]
K
VCO
t Low-pass Filter
VCO
M
÷
Frequency
Divider
n
i
(t)
n
PD
(t)
n
F
(t)
n (t)
n
D
(t)
Input
Fig. 1.
The functional block diagram of PLL in the presence of all the relevant sources.
;
Ln
a
n
t
n
n
d
d
a
n
1 tn
1 n
1 d
d a
0
+
+
+ L
m
b
m
t
m
m
d
d
b
m
1 t
m
1 m
1 d
d b
0
+
+
+ L
n
( )
t
d
d L
n
( )
t
d
d in
L
n
( )
d n dt
--------
GL
m
( )
f
PD ( )
[
]
=
in
f
PD ( )
n t
( )
Analysis of Jitter due to Power-Supply Noise in Phase-Locked Loops
Payam Heydari, Massoud Pedram
Dept. of EE-Systems, University of Southern California
Los Angeles, CA 90089 and an equivalent circuit to represent the switching activities in var-
ious functional blocks. The package-level model is mainly domi-
nated by the large chip-package interface inductance, the on-chip
power bus model is dominated by the wire resistance. The noise
introduced by simultaneous switching of the output drivers can be
very large since driving large external capacitances generates large
current surges. Fig. 2.a. depicts the HSPICE simulation of the P/G
bounce due to simultaneous switching of ve off-chip drivers with-
out using the decoupling capacitor. Fig. 2.b shows the supply noise
in the presence of an on-chip decoupling capacitor of 10pF across
each output buffer. The device model parameter is taken from
TSMC 0.25
µ
single-poly, ve-metal process technology provided
by MOSIS which uses BSIM3v3 MOS model.
The main effect of
the on-chip decoupling capacitor is that it forces the same uc-
tuations to appear on both the on-chip power and ground wires.
If the decoupling capacitor is made much larger than the
switched capacitances, then the on-chip switching noise can be
effectively eliminated. Adding the decoupling capacitor, how-
ever, is less efcient for most off-chip drivers [3]. Therefore the
circuit will always experience the bounce effect on the power
and ground busses.
Fig. 2.
The power-supply noise for ve identical output drivers switching simulta-
neously. (a) Decoupling capacitor: 2pF (b) Decoupling capacitor: 100pF.
Fig. 3. shows a circuit model for power supply noise caused by
switching in the internal circuitry and the output drivers. The peak
amplitude of the supply noise is a function of the number of switch-
ing circuits switching simultaneously and the switching activities of
the internal circuitry which itself depends on the nature and statis-
tics of the input signals. Power supply noise can thus be modeled as
a stochastic process with independent random variables which can
in turn be modeled as a Gaussian stochastic process [9]. If one
could assume that the switching noise waveforms propagate to the
supply lines of the PLL with the same propagation delay regardless
of the distance of the switching gates from the PLL and since the
decoupling capacitors cannot completely smooth out the spikes
from the supply and ground line completely, then the supply noise
can be expressed as a train of narrow triangular waveforms with
random amplitude which are apart from one another by half the
clock period. For the realistic case of different propagation delays,
the supply noise is best modeled as a train of trapezoidal wave-
forms. The pulse width is a random process and is a depends on the
number of switching circuits at a single clock period. The pulse
width is still small that the power supply noise can be modeled as
an impulse train with a uni