acing=0 width=100%>Yahoo! is not affiliated with the authors of this page or responsible for its content.
On-chip samplers for test and debug of asynchronous circuits
On-chip samplers for test and debug of asynchronous circuits
Frankie Liu, Ron Ho, Robert Drost, and Scott Fairbanks
Sun Microsystems Laboratories, Menlo Park, CA
ron.ho@sun.com
Abstract
On-chip high-bandwidth sampling circuits supplement
traditional test and debug techniques by non-invasively
probing analog voltages for off-chip measurement. Exist-
ing circuits rely on sub-sampling techniques and thus re-
quire a synchronous clock. We extend these ideas to asyn-
chronous circuits by combining an analog sampling head
with a variable delay element and activating this circuit
with an asynchronously triggered event. Repeated trigger-
ing events with different delays emulate sub-sampling. Sim-
ulations in a 180nm technology of SRAM timing margins
and GasP control failure modes show this technique can
probe asynchronous signals with high delity.
1. Introduction
The increase in speed and complexity of integrated cir-
cuits raises the importance of test and debug, especially un-
der process variations, power supply uctuations, and ther-
mal loads. VLSI scaling trends make test and debug more
critical but also more difcult, as environmental conditions
continue to worsen and designers adopt increasingly aggres-
sive circuits that require innovative testing schemes.
Test and debug is an expensive, time-consuming task in
which automated testers run code fragments on a chip and
compare the chips output to a stored expected response.
Designers deal with errors, in the parlance of debug teams,
by rst root-causing the problem, then onion-peeling
back layers of the design to search for other rats.
1
Bugs
lead to design xes and new chip spins, errata or features.
To nd the root cause of a test error, designers tradition-
ally rely on a combination of inference measurements, built-
in self-test (BIST) circuits and external probes (Figure 1).
All have limitations.
Inference measurements plot chip
functionality versus power supply and frequency. These
shmoo gures
2
reveal circuit behavior through power and
1
On a ship, if you see one rat, you can be sure there are many other rats.
The analogy with an integrated circuit and a design error follows directly.
2
Originally named after the LilAbner comic strip character, these are
frequency trends, but cannot directly measure specic cir-
cuits.
BIST interfaces generate inputs to specic logic
blocks and directly check the resulting outputs for func-
tional or timing faults [1, 5]. However, because they use
scan chains to feed inputs and to store outputs, they can
make such tests based only on digital logic values. Exter-
nal probes offer direct measurements of analog voltages at
nodes of interest, using electron beams, mechanical probes,
or laser probes [4]. However, such probing requires either
invasive techniques, test setups incompatible with packaged
parts, or both.
To supplement these techniques, designers have also
used on-chip high-bandwidth analog samplers that can
probe specic nodes in a packaged part. These circuits are
placed at nodes known to require post-fabrication probing,
or opportunistically dropped onto critical circuits in case
their fabricated performance misses specications. Such
analog BIST probe circuits have found use in power sup-
ply monitoring [11], memories [10], and interconnect eval-
uation [12].
Analog probe circuits rely on well-known sub-sampling
techniques to transfer high-bandwidth information off the
chip, but these techniques require a synchronous clock. In
this paper, we extend these methods to probe asynchronous
circuits, by combining an analog sampling head with a
variable delay element and activating this circuit with an
asynchronously triggered event. Repeated triggering events
with different delays emulate sub-sampling. Simulations in
a 180nm technology of SRAM timing margins and GasP
control failure modes show this technique can probe asyn-
chronous signals with high delity.
2. Sub-sampling circuits
In order to introduce the basic circuit operation, we rst
discuss a particular type of synchronous sub-sampling cir-
cuit used in analog probes [9, 6]; our asynchronous sam-
pler is based on this circuit. In these systems, an on-chip
sampling head that presents a very small load to the tested
often misspelled schmoo plots.
13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)
0-7695-2771-X/07 $20.00 � 2007 (a) Example shmoo plot, showing behavior in-
dicating an RC speedpath: as the period de-
creases, the chip fails the test no matter how
high the voltage is raised.
(b) BIST circuits surround logic
blocks, generating random inputs
and checking output signatures.
(c) Laser voltage probes shoot lasers at
the back of a thinned chip, and rely on
silicons change in reectivity with volt-
age. Figure taken from Eiles [4].
Figure 1. Traditional test and debug techniques.
circuit provides the functionality of an analog ip-op (Fig-
ure 2): when Sclk rises, a facsimile of the voltage under test
transfers to the gate of a PMOS transistor. This implemen-
tation allows sampling of voltages near ground; sampling
full-swing voltages can be done by boosting the gate volt-
ages of the NMOS passgates and the source voltage of the
PMOS transistor to
V
dd
+V
t
. The PMOS transistor converts
the sampled voltage into a current, which gets multiplied
up using two current mirrors and then driven off-chip into
the resistive input of an oscilloscope. An option on such
samplers, not shown here, adds a source-follower on the in-
puts. This prevents the sampler from disturbing the node
under test, especially if it is only weakly driven. Multiple
samplers are typically muxed together between their cur-
rent mirrors, with the samplers chosen through a JTAG/scan
chain interface, thus saving pins.
Figure 2. Basic sampling circuit
To determine how input voltages translate into output
currents, a separate calibration path (Vcal in Figure 2) al-
lows the system to sample an externally applied DC voltage.
Sweeping this calibration voltage gives the relationship be-
tween input voltage and output current for each individual
sampler. If the input uses a source-follower as a buffer, an-
other source-follower on the calibration input allows rst-
order cancellation of the resulting voltage shift.
2.1
Sampling modes
The sampler can be run in two different modes. In a
visual mode, the sampler clock and chip clock periods
differ by a very small amount, and the chip is set to repeat
the same operation every clock cycle. For example, the chip
clock period may be set to 1nS and the sampler clock period
to 1.001nS. Each cycle, the sampler examines a new point
on the repetitive test waveform, so that over many cycles,
the sampler will walk across the test waveform. In our ex-
ample, sweeping the test voltage will produce 1000 differ-
ent sampling cycles, with each sampling step separated by
one picosecond. In this mode, the bandwidth of the sampled
voltage is limited by potentially incomplete charge-sharing
through the analog ip-op (between nodes
A and B in Fig-
ure 2). However, the benet of visual mode is that the output
is a replica of the internal waveform, albeit at an expanded
time scale: if we dial out the time base of our output os-
cilloscope to the beat frequency of the two clocks (1MHz
in our example), we will see a picture of the real on-chip
waveform, which can then be captured and calibrated.
In the second, accurate, mode, the sampler clock and
the chip clock have the same frequency, although not the
same phase. Over many cycles, the circuit continuously
samples the same test voltage, ensuring that the resulting
voltage on the PMOSs gate accurately reects the sampled
test voltage. The resulting output current can be recorded
and mapped back to an input voltage using the calibration
curves. Then, by stepping the phase of the sampler clock
relative to the chip clock, the sampler can map out another
voltage. By repeating this process, the sampler can even-
tually draw out a very accurate waveform. Figure 3 shows
these two modes graphically.
13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)
0-7695-2771-X/07 $20.00 � 2007 Visual mode: sampler clock period > chip clock period
Accurate mode: sampler clock period = chip clock period
Figure 3. Samplers in two modes
If the systems periodicity is at multiples of the chip
clock, the sampling clock can be run at fractions of the chip
clock. For example, if the node under test repeats every
other clock cycle, the sampling clock should run at half the
speed of the chip clock (minus a small difference if in visual
mode) in order to capture the desired signal.
We have used samplers of this variety in a number of our
test chips and have found them useful not only in debugging
synchronous circuits, but also for testing timing margings,
testing voltage margins, and generating plots for design re-
views and publications [7],[8].
2.2
Asynchronous sub-sampling circuits
In the synchronous accurate mode described above, the
sampling head captures the test voltage a xed delay after
each chip clock edge. After measuring the resulting out-
put current, the user increases this xed delay by a small
amount and takes another m