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82C88 1
®
82C88
CMOS Bus Controller
The Intersil 82C88 is a high performance CMOS Bus
Controller manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C88 provides the
control and command timing signals for 80C86, 80C88,
8086, 8088, 8089, 80186, and 80188 based systems. The
high output drive capability of the 82C88 eliminates the need
for additional bus drivers.
Static CMOS circuit design insures low operating power. The
Intersil advanced SAJI process results in performance equal
to or greater than existing equivalent products at a significant
power savings.
Pinouts
20 LD PDIP, CERDIP
TOP VIEW
20 LD PLCC, CLCC
TOP VIEW
Features
Compatible with Bipolar 8288
Performance Compatible with:
- 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . (5/8MHz)
- 80186/80188. . . . . . . . . . . . . . . . . . . . . . . . . . (6/8MHz)
- 8086/8088. . . . . . . . . . . . . . . . . . . . . . . . . . . . (5/8MHz)
- 8089
Provides Advanced Commands for Multi-Master Busses
Three-State Command Outputs
Bipolar Drive Capability
Scaled SAJI IV CMOS Process
Single 5V Power Supply
Low Power Operation
- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
µA (Max)
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 1mA/MHz (Max)
Operating Temperature Ranges
- C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
- M82C88 . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Pb-Free Plus Anneal Available (RoHS Compliant)
11
12
13
14
15
16
17
18
19
20
10
9
8
7
6
5
4
3
2
1
IOB
CLK
ALE
GND
DT/ R
AEN
MRDC
AMWC
MWTC
S1
V
CC
MCE/PDEN
DEN
CEN
IORC
AIOWC
IOWC
INTA
S0
S2
4
5
6
7
8
9
10 11 12 13
3
2
1
20 19
15
14
18
17
16
ALE
DT/ R
AEN
MRDC
AMWC
GND
IO
RC
AIOWC
IO
WC
MWT
C
V
CC
IO
B
CLK
S1
S0
DEN
CEN
MCE/PDEN
INTA
S2
Ordering Information
PART
NUMBER
PART
MARKING
PACKAGE
TEMP
RANGE
(°C)
PKG.
DWG. #
CP82C88
CP82C88
20 Ld PDIP
0 to +70
E20.3
CP82C88Z
(Note)
CP82C88Z
20 Ld PDIP
(Pb-free)
0 to +70
E20.3
CP82C88-10 CP82C88-10 20 Ld PDIP
0 to +70
E20.3
IP82C88
IP82C88
-40 to +85
E20.3
CS82C88
CS82C88
20 Ld PLCC
0 to +70
N20.35
IS82C88
IS82C88
-40 to +85
N20.35
CD82C88
CD82C88
20 Ld
CERDIP
0 to +70
F20.3
ID82C88
ID82C88
-40 to +85
F20.3
MD82C88/B
MD82C88/B
-55 to +125
F20.3
8406901RA
8406901RA
SMD#
F20.3
MR82C88/B
MR82C88/B 20 Pad CLCC -55 to +125
J20.A
84069012A
84069012A
SMD#
J20.A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Data Sheet
FN2979.2
August 25, 2005
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners. 2
FN2979.2
August 25, 2005
Functional Diagram
Pin Description
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
V
CC
20
V
CC
: The +5V power supply pin. A 0.1
µF capacitor between pins 10 and 20 is recommended for decoupling.
GND
10
GROUND.
S0, S1, S2
19, 3, 18
I
STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors. The
82C88 decodes these inputs to generate command and control signals at the appropriate time. When Status pins
are not in use (passive), command outputs are held HIGH (See Table1).
CLK
2
I
CLOCK: This is a CMOS compatible input which receives a clock signal from the 82C84A or 82C85 clock
generator and serves to establish when command/control signals are generated.
ALE
5
O
ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address latches. This signal is
active HIGH and latching occurs on the falling (HIGH to LOW) transition. ALE is intended for use with transparent
D type latches, such as the 82C82 and 82C83H.
DEN
16
O
DATA ENABLE: This signal serves to enable data transceivers onto either the local or system data bus. This
signal is active HIGH.
DT/R
4
O
DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through the transceivers. A HIGH
on this line indicates Transmit (write to I/O or memory) and a LOW indicates Receive (read from I/O or memory).
AEN
6
I
ADDRESS ENABLE: AEN enables command outputs of the 82C88 Bus Controller a minimum of 110ns (250ns
maximum) after it becomes active (LOW). AEN going inactive immediately three-states the command output
drivers. AEN does not affect the I/O command lines if the 82C88 is in the I/O Bus mode (IOB tied HIGH).
CEN
15
I
COMMAND ENABLE: When this signal is LOW all 82C88 command outputs and the DEN and PDEN control
outputs are forced to their Inactive state. When this signal is HIGH, these same outputs are enabled.
IOB
1
I
INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 82C88 functions in the I/O Bus mode.
When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus and System Bus sections).
AIOWC
12
O
ADVANCED I/O WRITE COMMAND: The AIOWC issues an I/O Write Command earlier in the machine cycle to
give I/O devices an early indication of a write instruction. Its timing is the same as a read command signal.
AIOWC is active LOW.
IOWC
11
O
I/O WRITE COMMAND: This command line instructs an I/O device to read the data on the data bus. The signal
is active LOW.
IORC
13
O
I/O READ COMMAND: This command line instructs an I/O device to drive its data onto the data bus. This signal
is active LOW.
V
CC
GND
COMMAND
SIGNALS
MULTIBUS
TM
CONTROL
INPUT
IOB
CEN
CLK
AEN
CONTROL
SIGNAL
GENERATOR
DEN
ALE
DT/R
MCE/PDEN
COMMAND
SIGNAL
GENERATOR
AIOWC
IOWC
AMWC
MWTC
MRDC
IORC
S2
S1
S0
INTA
ADDRESS LATCH,
DATA TRANSCEIVER,
AND INTERRUPT
CONTROL SIGNALS
CONTROL
LOGIC
STATUS
DECODER
82C88
82C88 3
FN2979.2
August 25, 2005
Functional Description
The command logic decodes the three 80C86, 8086, 80C88,
8088, 80186, 80188 or 8089 status lines (S0, S1, S2) to
determine what command is to be issued (see Table 1).
I/O Bus Mode
The 82C88 is in the I/O Bus mode if the IOB pin is strapped
HIGH. In the I/O Bus mode, all I/O command lines IORC,
IOWC, AIOWC, INTA) are always enabled (i.e., not
dependent on AEN). When an I/O command is initiated by
the processor, the 82C88 immediately activates the
command lines using PDEN and DT/R to control the I/O bus
transceiver. The I/O command lines should not be used to
control the system bus in this configuration because no
arbitration is present. This mode allows one 82C88 Bus
Controller to handle two external busses. No waiting is
involved when the CPU wants to gain access to the I/O bus.
Normal memory access requires a Bus Ready signal (AEN
LOW) before it will proceed. It is advantageous to use the
IOB mode if I/O or peripherals dedicated to one processor
exist in a multi-processor system.
System Bus Mode
The 82C88 is in the System Bus mode if the IOB pin is
strapped LOW. In this mode, no command is issued until a
specified time period after the AEN line is activated (LOW).
This mode assumes bus arbitration logic will inform the bus
controller (on the AEN line) when the bus is free for use.
Both memory and I/O commands wait for bus arbitration.
This mode is used when only one bus exists. Here, both I/O
and memory are shared by more than one processor.
Command Outputs
The advanced write commands are made available to initiate
write procedures early in the machine cycle. This signal can
be used to prevent the processor from entering an
unnecessary wait state.
INTA (Interrupt Acknowledge) acts as an I/O read during an
interrupt cycle. Its purpose is to inform an interrupting device
that its interrupt is being acknowledged and that it should
place vectoring information onto the data bus.
The command outputs are:
MRDC - Memory Read Command
MWTC - Memory Write Command
IORC - I/O Read Command
IOWC - I/O Write Command
AMWC - Advanced Memory Write Command
AIOWC - Advanced I/O Write Command
INTA - Interrupt Acknowledge
AMWC
8
O
ADVANCED MEMORY WRITE COMMAND: The AMWC issues a memory write command earlier in the machine
cycle to give memory devices an early indication of a write instruction. Its timing is the same as a read command
signal. AMWC is active LOW.
MWTC
9
O
MEMORY WRITE COMMAND: This command line instructs the memory to record the data present on the data
bus. This signal is active LOW.
MRDC
7
O
MEMORY READ COMMAND: This command line instructs the memory to drive its data onto the data bus. MRDC
is active LOW.
INTA
14
O
INTERRUPT ACKNOWLEDGE: This command line tells an interrupting device that its