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28 March 2007
1
Revision A
CRaTER Digital Subsystem Functional Specification
Revision A
28 March 2007
Dwg. No.: 32-03010
References.
1. Spacecraft to CRaTER Data Interface Control Document, (32-02001.01), Revision E, January 12, 2007
2. CRaTER Analog to Digital Subsystem Electrical Interface Control Document, (32-02052), Revision B,
5/17/2006
Rev
ECO
Date
Change Summary
Author
A
32-205
28 Mar 2007
Initial Formal Release
(corresponds to FPGA Version 3)
D. Gordon 28 March 2007
2
Revision A
Pre-Release Revision History
Rev
ECO
Date
Change Summary
Author
01
32-114
19 APR 2006
Initial Draft
D. Gordon
02
32-121
05 May 2006
Corrections to bit/byte ordering; addition of testmode;
changed Telem. Stall Counter to Good Event Counter
D. Gordon
03
32-141
30 May 2006
Bias Clocks removed, Secondary bias voltage control signal
added, Analog Voltage Monitor added
D. Gordon
04
32-178
05 Oct 2006
Correction to DetEnb field ordering in Secondary Science
Testmode enhancements
Addition of Relay Control for 1553 bus transformer
Default Polarity of Test Pulser Clocks changed
(corresponds to FPGA Version 1)
D. Gordon
05
32-190
06 Dec 2006
Pulser Low Frequency changed to 8Hz
Housekeeping values averaged
(corresponds to FPGA Version 2)
D. Gordon
06
32-204
27 Feb 2007
Pulser Clock is timed
GATE is eliminated (held high); RAMP is extended
(corresponds to FPGA Version 3)
D. Gordon 28 March 2007
3
Revision A
Table of Contents
1.0 Introduction........................................................................................ 4
2.0 CDC Subsystems ...................................................................................5
2.1
Timing Control ..........................................................................5
2.2 1553 Bus Control........................................................................5
2.2.1 Command Interface.........................................................5
2.2.2 1553 Telemetry Interface .................................................7
2.3 Housekeeping Data Controller ................................................11
2.4 Test Pulser Interface..................................................................11
2.5 LLD Threshold Levels ...............................................................12
2.6 Event Processing ......................................................................12
2.7 Event Counters ........................................................................ 13
2.7.1 Event Reject Counter .................................................... 13
2.7.2 Total Event Counter...................................................... 13
2.7.3 Good Event Counter..................................................... 13
2.7.4 Singles Counter(s) ......................................................... 13
2.8 Primary Science Packet Generation ........................................14
2.9 Test Mode.................................................................................14
2.10 Analog Voltage Monitor......................................................... 15 28 March 2007
4
Revision A
1.0 Introduction
The CRaTER Digital Control (CDC) is a subsystem of the CRaTER (Cosmic Ray Telescope for
the effects of Radiation), an instrument in the LRO (Lunar Reconnaissance Orbiter). The front-
end interfaces to the analog electronics, receiving the linear and trigger outputs (preprocessed by
the Analog Processing Board) corresponding to six solid state detectors. The backend interfaces
to the spacecraft via a 1553 bus interface. A radiation tolerant field programmable logic array
(FPGA) houses the digital circuitry that receives commands, collects the digitized events, filters
the events in accordance with the preset configuration, and formats/sends telemetry packets.
FIGURE 1. CRaTER Digital Subsystem: Overall Block Diagram
Figure 1 shows an overview of the CRaTER Digital Subsystem. Commands arrive at the 1553
Bus Interface, the top right module. Commands typically set values internal to the Crater Data
Control (CDC) FPGA that relate to event acceptance criteria. A few commands directly set exter-
nal controls, such as the Test Pulser DAC and Bias Voltage Enable. Events, processed and pack-
etized by the CDC, are forwarded to the S/C via the 1553 bus interface.
The Analog Signal Processing subsystem consists of six identical slices. Each slice receives a
detector signal, holds the peak, and compares it to a set threshold. A/D conversion follows peak
detection if any of the events cross threshold. Additionally, six digital signals indicating detector
specific threshold crossings are driven by the Analog Processing board. A test pulser DC level
and clocks, configurable via the command interface, facilitate testing.
The Housekeeping Data Controller regularly acquires data from an on-board ADC, maintaining a
register file which the 1553 Bus Interface Module periodically reads.
The Master Clock (16 MHz), generated via an on-board oscillator, drives the FPGA and the 1553
Bus Protocol IC.
This document describes the FPGA functionality, referring to the external circuitry only as it
relates to the FPGA design.

225VN
75VN
5VN
VCC
225VP
5VP
75VP
5VN
5VP
1553_A
1553_B
S/C
1HZ
CLOCK
AE
I/F
S/C
I/F
Crater Analog Housekeeping
28VDC +
RETURN
to Analog Housekeeping
Also sent to AE Subystem: Vcc
(5V) and Digital Ground
t
RTD
1553 Bus
Protocol
Controller -
Transceiver
Diff.Rcvr
SCLK
RESET
+
-
Spacecraft Data Interface
1553Dat[15:0]
1553AdrCntl[22:0]
A-
A+
B+
B-
1PPS_+
CLK1HZ
CLK16M
Reset
1PPS_-
Peak Detect/Hold
ADC
Vthreshold
Comparator
x6
x6
x6
Analog Signal Processing
DetSigIn[5:0]
ADC-CntlDat[5:0]
DetTrig[5:0]
PDReset[5:0]
ThrThin
ThrThick
Analog
Mux
ADC
Precondition
Filter/Scale
x2
x2
Housekeeping
HSKPIN[23:0]
MADRSEL[4:0]
ADC-CntlDat[1:0]
CDM-FPGA
SRAM
Power-On
Reset
OSC
Crater Data Control
DetTrig[5:0]
1553Dat[15:0]
ADC-CntlDat[5:0]
1553AdrCntl[22:0]
CLK16M
CLK1HZ
ECALPWM
HWReset
ECAL-PCK[1:0]
HADRSEL[4:0]
HADC-CntllDat[1:0]
PDReset[5:0]
LLDTHKPWM
LLDTHNPWM
SngCnt[5:0]
BIASVENB
BIASVCTL
EMI
Filter
DC to DC Conversion
5V
28VDC_+
28VDC_-
5V_+
5V_-
GND
BiasVEnb
225V_+
75V_+
BiasVCtl
PWM to DC
Buffer
0 - 4V.
8 bit
Test Pulse I/F
PCKOUT[1:0]
PCK[1:0]
ECAL-DC
ECALPWM
PWM to DC
- 0.05 - 1.4V.
8 bit
PWM to DC
- 0.05 - 1.4V.
8 bit
LLD Threshold
LLDTHIN-DC
LLDTHINPWM
LLDTHKPWM
LLDTHCK-DC
DetSig[5:0]
ThinDetBias
ThickDetBias
RT_P
RT_N
SigGnd
AETemp[1:0]
5VP
5VN
TP-PCK[1:0]
P-LEVEL
SngCnt[5:0] 28 March 2007
5
Revision A
2.0 CDC Subsystems
2.1 Timing Control
A 1PPS (1 second clock) is received from the Spacecraft.
Edge detect circuitry converts the 1 second clock (leading edge) into a one clock-pulse wide tick
(TK1S) that is forwarded to all the CDC logic subsystems. TK1S loads the time registers, and
causes the pre-staged commands to be registered into the active stage.
The S/C forwards a Time of Next Sync Pulse every second that updates the CDC seconds and
subseconds registers. If the Time of Next Sync Pulse Command is not received during any
one-second interval, the seconds and subseconds register are cleared by the following TK1S.
These registers are a component of the secondary header, included with all three type of telemetry
packets (Housekeeping, Secondary Science and Primary Science).
A division of the Master Clock serves as a backup for the spacecraft 1 second clock. Each TK1S
clears the divider. In the absence of the 1 second clock, the counter will produce its own TK1S
with a period of 1.05 seconds. An indication of the TK1S generator (internal versus external) is
provided in the 1553 Telemetry Secondary Headers.
The timing control subsystem provides a relay control, asserted between 1 - 2.5 seconds following
the deassertion of the power on reset signal. The relay control assures that the 1553 bus trans-
formers are disconnected at power-on due to a potential overcurrent condition.
2.2 1553 Bus Control
The 1553 module consists of two autonomous subsystems: a command receiver/parser and a
telemetry packet builder/transmitter. An external Remote Terminal IC (BU-63705) serializes/
deserializes and performs error detection on the incoming messages. CDC logic strips the rele-
vant data out of the commands and supplies data for telemetry.
CDC operates as a Remote Terminal (RT) at address 0x10 (16 decimal), set via BU-63705 inputs
RTADDR(4:0) (= 10000) and RTADDRP (=0) (the parity bit). The BU-63705 responds only to
commands and requests for telemetry that match the set RT address. Within the RT address,
CRaTER responds to eight subaddress for commands (see Section 2.2.1) and three for telemetry
(seeSection 2.2.2). Transactions directed to unused subaddresses will be serviced (i.e. data
requests will be acknowledged); however, there will be no response from the subsystem, and data
supplied (in response to telemetry requests) is indeterminate.
The BU-63705 configuration disables both broadcast mode and dynamic bus control.
2.2.1 Command Interface
Commands, listed below, arrive via the 1553 Bus. Since each command type is directed to a
unique 1553 bus subaddress, each is allocated its own 1553 bus message. CDC prelatches the
command word based on the word-count and subaddress output by the BU-63705. The headers
and BU-63705 error flags are not monitored. CDC just strips the data word(s) relevant to each
command type, and preloads them in expectation of the GBR (Good Block Received, status sig-
nal from BU-63705) strobe. Command reception is not finalized unless a GBR assertion follows 28 March 2007
6