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Comparisons of Various Scan Delay Test Techniques Comparisons of Various Scan Delay Test Techniques

Center for Reliable Computing
Stanford University
December 2005
Task ID: 1175.001
Donghwi Lee and Edward J. McCluskey




Abstract

Chips that produce correct results under operating conditions are called good chips.
Some good chips may fail structural tests applied via scan chains (also called overkill
chips). A reduction in supply voltage (also called supply voltage droop) due to the
resistance of power-ground network is called IR-drop. IR-drop is investigated as a potential
cause of overkill. IR-drop may slow down the speed of a chip unnecessarily, which could
result in failing the structural test even though the chip could operate correctly in normal
operation (i.e., overkill). In order to reduce the switching activity, test patterns can be
generated such that dont-care bits are filled with the last significant bit (also called repeat-
fill test patterns). Our experiments show that repeat-fill test patterns reduce the occurrence
of overkill by 58%, but increase the number of test escapes by 50%.
A new technique to reduce potential overkill due to IR-drop is presented. Compared to
the normal transition delay test set, the proposed technique was able to reduce the
occurrence of overkill by 25% without increasing test escapes. The proposed test set has the
same number of patterns as the normal transition delay test set while the repeat-fill test set
has 2.3 times larger in test set length compared to the normal transition delay test set. Test
time of proposed technique is 1.3 times longer than test time of the normal transition delay
ii
test set. In the repeat-fill test set, test time is 2.3 times longer than test time of the normal
transition delay test set.
iii

TABLE OF CONTENTS
LIST OF TABLES................................................................................................................ v
LIST OF FIGURES............................................................................................................vii
1 Introduction .................................................................................................................. 1
1.1
Sources of overkill.................................................................................................. 1
1.2 Outline .................................................................................................................... 4
2 Test
Chip ....................................................................................................................... 5
3 Test
flows....................................................................................................................... 7
3.1 Production
test
flow................................................................................................ 7
3.2
Experiment test flow............................................................................................... 7
4
Definitions, Test chip categories, and Results............................................................ 9
4.1 Definitions .............................................................................................................. 9
4.1.1 Test
escape...................................................................................................... 9
4.1.2 Rated-speed
failure......................................................................................... 9
4.1.3 Slow-speed
failure .......................................................................................... 9
4.1.4 Weak
suspect .................................................................................................. 9
4.1.5 Overkill
candidate .......................................................................................... 9
4.1.6 Defective
chip................................................................................................. 9
4.2
Results of test chip classification ........................................................................... 9
5
Switching activity of test patterns ............................................................................. 11
5.1
Switching activity of scan-based test patterns...................................................... 11
5.2
Transition delay test set ........................................................................................ 13
5.2.1 Launch-on-capture
and
launch-on-shift transition delay test set.................. 13
5.2.2
Launch-on-capture test set with idle cycles.................................................. 15
5.3 Delay
size ............................................................................................................. 17
5.4 Test
setup.............................................................................................................. 17
5.4.1
Repeat-fill LOC test set generation .............................................................. 17
5.4.2
LOC-IC test set generation........................................................................... 18
iv
5.4.3 Test
flow....................................................................................................... 18
5.5 Experimental
results ............................................................................................. 20
5.5.1
Repeat-fill LOC test set ................................................................................ 20
5.5.2
LOC test sets with idle cycles after scan enable signal transition................ 21
5.5.3
LOC test sets with idle cycles before scan enable signal transition ............. 22
5.5.4
Delay size and minimum operating voltage ................................................. 22
5.5.5
Test time cost................................................................................................ 24
5.5.6
Comparisons of scan-based LOC test sets.................................................... 25
6 Conclusions ................................................................................................................. 27
7 Acknowledgements ..................................................................................................... 29
References ........................................................................................................................... 31

v
LIST OF TABLES
Table 1 Delay of paths a defect .............................................................................................. 2
Table 2 Delay of paths without a defect................................................................................. 3
Table 3 Characteristics of test chips....................................................................................... 5
Table 4 Test conditions .......................................................................................................... 8
Table 5 Structural test sets for the experiment test flow ........................................................ 8
Table 6 ELF13 test chip classification ................................................................................. 10
Table 7 Summary of LOC test sets....................................................................................... 19
Table 8 Experimental results base LOC vs. repeat-fill LOC............................................. 20
Table 9 Experimental results on LOC-IC test sets ............................................................... 21
Table 10 Test time comparison ............................................................................................ 25
Table 11 Comparisons of scan-base LOC test sets .............................................................. 26

vi

vii
LIST OF FIGURES
Figure 1 Multi-cycle path - example ...................................................................................... 1
Figure 2 Long false path - example ........................................................................................ 2
Figure 3 Production test flow ................................................................................................. 7
Figure 4 Experiment test flow ................................................................................................ 8
Figure 5 SPICE simulations Delay vs. temperature .......................................................... 12
Figure 6 SPICE simulations Delay vs. supply voltage...................................................... 13
Figure 7 Timing diagrams of transition delay test patterns.................................................. 14
Figure 8 Timing diagram of LOC-IC transition delay test pattern....................................... 15
Figure 9 Flowchart of LOC-IC test set generation............................................................... 16
Figure 10 Flowchart of reduced faults collection................................................................. 18
Figure 11 Histogram of added delay ...........................