J-Type
Voltage Controlled Crystal Oscillator
Product is compliant to RoHS directive and fully compatible with lead free assembly Features
· Output Frequencies from 1.024 MHz to 170.000 MHz · +3.3 or +5.0 volt options · Small 14mm x 9mm J-type Package · CMOS or PECL Outputs · Low phase noise and custom options · 0/70° C or ­40/85° C operating temperature · Tri-State output (CMOS) Enable/Disable (PECL) Applications
· Clock Smoothing The J-type Voltage Controlled Crystal Oscillator · Frequency Translation · SONET, SDH, ATM, DSLAM, ADM Description
The J-type voltage controlled crystal oscillator expands VI's advanced VCXO performance capabilities while adhering to a package footprint compatible with the industry-common J-lead package. The J-type VCXO is a quartz stabilized square wave generator with either a CMOS output for driving CMOS/TTL loads or a PECL output. The device is packaged in a 6 pin J-lead ceramic package and is hermetically sealed with a grounded conductive lid. The first section of this data sheet covers the performance/packaging/tape and reel/ordering information for the CMOS version and then the information for the PECL option follows. Table of Contents Page 2- 6 -- CMOS Page 7- 11 -- PECL Vectron International 267 Lowell Rd. Hudson, NH 03051 Tel:1-88-VECTRON-1 e-mail: vectron@vectron.com J-Type Voltage Controlled Crystal Oscillator Table 1. Pin Out Information for the CMOS output Option
Pin 1 2 3 4 5 6 Symbol VC Tri-State1 GND Output CMOS/TTL select1,2 VCC Function VCXO Control Voltage TTL logic low disables output. TTL logic high, or no connect, enables output. Case and Electrical Ground VCXO Output TTL logic low optimizes symmetry for CMOS. TTL logic high, or NC, optimizes symmetry for TTL Power Supply Voltage (5.0 V or 3.3 V ±10%)
6 5 4 TOP VIEW 1 2 3 1. Standard option. Tri-State can be connected to pin 5 and CMOS/TTL select would be on pin 2. 2. Output is HCMOS. For frequencies >12MHz, this option optimizes symmetry for either CMOS or TTL thresholds. Ground this pin for frequencies < 12MHz. Table 2. Electrical Performance @ 25°C for the CMOS output option
Parameter Supply Voltage 1, +5 volt option +3.3 volt option Supply Current Center Frequency, see ordering information Operating Temperature, see ordering info Absolute Pull Range over the operating temperature range, aging and power supply Vc= 0.5 to 4.5 or 0.3 to 3.0 V see ordering information for options Gain Transfer (Frequency vs. Control Voltage) Output Level High2 Output Level Low2 Output Rise/Fall Time2 Duty Cycle3, see ordering info Input Leakage Control Voltage Modulation Bandwidth RMS Jitter, 77.760MHz RMS Jitter, 77.760MHz, 12kHz to 20MHz Maximum Control Voltage Maximum Supply Voltage Storage Temperature Soldering Temp./Time Symbol Minimum Typical Maximum 4.5 5.0 5.5 3.0 3.3 3.6 10mA + 0.25mA per MHz, typical 1.024 77.760 0/70, -40/85 ±50 to ±100 Units V V MHz °C ppm FN TOP APR KV VOH VOL tR/ tF SYM IL BW 0.8*Vcc Positive 45/55 or 40/60 10 3 51.840MHz. 4. Note: Not all combinations are possible. Example: JDUGCKTN 77.76 = 3.3 volt, VCXO@77.760, ±50 ppm APR, 0/70°C, 40/60% Symmetry, CMOS, Tri-State on pin 2. Vectron International 267 Lowell Rd. Hudson, NH 03051 Tel:1-88-VECTRON-1 5 e-mail vectron@vectron.com J-Type Voltage Controlled Crystal Oscillator Table 7. Standard Frequencies, in MHz, for CMOS output option
1.024 3.686 6.144 8.448 14.318 19.440 27.000 38.880 52.000 1.544 4.000 6.176 10.000 15.360 20.000 30.000 40.000 62.208 2.000 4.032 6.312 12.000 15.440 20.480 32.000 40.960 65.536 2.048 4.096 6.400 12.288 16.000 24.000 32.768 44.736 77.760 3.088 4.434 8.000 12.352 16.384 24.576 34.368 50.000 155.5201 3.580 5.000 8.192 13.000 18.432 24.704 35.328 51.840 1. Uses a PLL multiplier, jitter is 25ps rms typical vs 3ps typical for a HFF design Other frequencies available upon request. Table 8. Pin Out Information for the PECL output option
Pin 1 2 3 4 5 6 Symbol VC N/C or E/D2 GND Output COutput VCC Function VCXO Control Voltage No Connect or Output Disable Case and Electrical Ground VCXO Output VCXO Complementary Output Power Supply Voltage (5.0 V or 3.3 V ±10%)
6 5 4 TOP VIEW 1 2 3 . By setting OD high, the outputs are disabled and OUT is held low while Complementary OUT is held high. Output is enabled if E/D < VCC-1.6V, 2. See ordering information for enable/disable option. Table 9. Electrical Performance @ 25°C for the PECL output option
Parameter Supply Voltage 1, +5 volt option +3.3 volt option Supply Current Center Frequency, see ordering information Operating Temperature, see ordering info Absolute Pull Range over the operating temperature range, aging and power supply. Vc= 0.5 to 4.5 or 0.3 to 3.0 see ordering information for options Gain Transfer (Frequency vs. Control Voltage) 2 Output Level High 2 Output Level Low Output Level High2 Output Level Low2 Output Rise and Fall Time2 Duty Cycle3, see ordering info Input Leakage RMS Jitter, 12kHz to 20 MHz, P option (HFF) Control Voltage Modulation Bandwidth Maximum Control Voltage Maximum Supply Voltage Storage Temperature Soldering Temp./Time Symbol Minimum Typical Maximum 4.5 5.0 5.5 3.0 3.3 3.6 frequency dependent 15 170 0/70, -40/85 ±32, ±50 Units V V MHz °C ppm FN TOP APR KV Positive VOH Vcc-1.025 Vcc-0.880 V VOL Vcc-1.810 Vcc-1.620 V Output Logic Levels for -40 to 85°C Operation VOH Vcc-1.085 Vcc-0.880 V VOL Vcc-1.830 Vcc-1.555 V tR/tf 1 ns SYM 45/55 % IL 0.1 mA