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TVS Diode Arrays
SCR Diode Array for ESD and Transient Overvoltage Protection
SP724
The SP724 is a quad array of transient voltage clamping circuits designed
to suppress ESD and other transient over-voltage events. The SP724 is
used to help protect sensitive digital or analog input circuits on data,
signal, or control lines operating on power supplies up to 20VDC.
The SP724 is comprised of bipolar SCR/diode structures to protect up
to four independent lines by clamping transients of either polarity to the
power supply rails. The SP724 offers very low leakage (1nA Typical) and
low input capacitance (3pF Typical). Additionally, the SP724 is rated to
withstand the IEC 61000-4-2 ESD specification for both contact and air
discharge methods to level 4.
The SP724 is connected to the sensitive input line and its associated
power supply lines. Clamping action occurs during the transient pulse,
turning on the diode and fast triggering SCR structures when the voltage
on the input line exceeds one VBE threshold above the V+ supply (or
one VBE threshold below the V- supply). Therefore, the SP724 operation
is unaffected by poor power supply regulation or voltage fluctuations
within its operating range.
Features
An Array of 4 SCR/Diode Pairs in 6-Lead SOT-23
ESD Capability per HBM Standards
- IEC 61000-4-2, Direct Discharge . . . . . . . . . . . . . . . . . 8kV (Level 4)
- IEC 61000-4-2, Air Discharge . . . . . . . . . . . . . . . . . . 15kV (Level 4)
- MIL STD 3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >8kV
Input Protection for Applications with Power Supplies Up to +20V
(Single-Ended Voltage), and ±10V (Differential Voltage)
Peak Current Capability
IEC 61000-4-5 (8/20µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3A
Single Pulse, 100µs Pulse Width . . . . . . . . . . . . . . . . . . . . . . . ±2.2A
Low Input Leakage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1nA Typical
Low Input Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3pF Typical
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . -40
o
C to 105
o
C
Applications
Microprocessor/Logic Input Protection
Data Bus Protection
Analog Device Input Protection
Voltage Clamp
Functional Block Diagram
Ordering Information
Pinout
PART Min.
Order
Qty.
NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
PKG. NO.
P6.064
3000
SP724AHT
-40 to 105
Tape and Reel
1
2
3
6
5
4
SP724
(SOT-23)
TOP VIEW
NOTES:
1. The design of the SP724 SCR/Diode ESD Protection Arrays is
covered by Littelfuse patent 4567500.
2. The full ESD capability of the SP724 is achieved when wired in a
circuit that includes connection to both the V+ and V- pins. When
handling individual devices, follow proper procedures for
electrostatic discharge.
2
V+
V-
IN
3, 4 AND 6
IN
1
5 247
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5
TVS DIODE ARRA
YS
TVS Diode Arrays
SP724
SCR Diode Array for ESD and Transient Overvoltage Protection
Absolute Maximum Ratings
Continuous Supply Voltage, (V+) - (V-). . . . . . . . . . . . . . . . . . . . . . . . . +20V
Forward Peak Current, IIN to VCC , GND
(Refer to Figure 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±2.2A, 100µs
ESD Ratings and Capability - See Figure 1, Table 1
Thermal Information
Thermal Resistance (Typical, Note 3) JA (
o
C/W)
SOT Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 220
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . .-65
o
C to 150
o
C
Maximum Junction Temperature . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . .. . . . . . . . . . . . . . . . 300
o
C
(SOT - Lead Tips Only)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Voltage Range,
V
SUPPLY
= [(V+) - (V-)] (Notes 4, 5)
V
SUPPLY
1
-
20
V
Forward Voltage Drop
IN to V-
V
FWDL
I
IN
= 1A (Peak Pulse)
-
2
-
V
IN to V+
V
FWDH
-
2
-
V
Input Leakage Current
I
IN
-10
1
10
nA
Quiescent Supply Current
I
QUIESCENT
V+ = 20V, V- = GND
-
-
100
nA
Equivalent SCR ON Threshold
(Note 6)
-
1.1
-
V
Equivalent SCR ON Resistance
V
FWD
/I
FWD
(Note 6)
-
1.0
- Input Capacitance
C
IN
-
3
-
pF
NOTES:
4. In automotive and other battery charging systems, the SP724 power supply lines should be externally protected for load dump and reverse battery. When
the V+ and V- Pins are connected to the same supply voltage source as the device or control line under protection, a current limiting resistor should be
connected in series between the external supply and the SP724 supply pins to limit reverse battery current to within the rated maximum limits.
5. Bypass capacitors of typically 0.01
µ
F or larger should be connected closely between the V+ and V- Pins for all applications.
6. Refer to the Figure 3 graph for definitions of equivalent SCR ON Threshold and SCR ON Resistance. These characteristics are given here
for information to determine peak current and dissipation under EOS conditions.
ESD Rating
ESD rating is dependent on the defined test standard. The evaluation
results for various test standards and methods based on Figure 1 are
shown in Table 1.3
The SP724 has a Level 4 rating when tested to the IEC 61000-4-2
Human Body Model (HBM) standard and connected in a circuit in which
the V+ and V- pins have a return path to ground. Level 4 specifies a
required capability greater than 8kV for direct discharge and greater than
15kV for air discharge.
The Modified MIL-STD-3015.7 condition is defined as an in-circuit
method of ESD testing, the V+ and V- pins have a return path to
ground.The SP724 ESD capability is greater than 8kV with 100pF
discharged through 1.5k . By strict definition of the standard MIL-
STD-3015.7 method using pin-to-pin device testing, the ESD voltage
capability is greater than 2kV.
For the SP724 EIAJ IC121 Machine Model (MM) standard, the ESD capa-
bility is typically greater than 1.8kV with 200pF discharged through 0k .
The Charged Device model is based upon the self-capacitance of the
SOT-23 package through 0k .
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = -40
o
C to 105
o
C, VIN = 0.5VCC , Unless Otherwise Specified
STANDARD
TYPE/MODE
R
D
C
D
±
V
D
IEC 61000-4-2
(Level 4)
HBM, Air Discharge
330 150pF
15kV
HBM, Direct Discharge
330 150pF
8kV
MIL-STD-3015.7 Modified HBM
1.5k 100pF
8kV Standard HBM
1.5k 100pF
2kV
EIAJ IC121
Machine Model
0k 200pF
400V
US ESD DS 5.3 Charged Device Model
0k NA
3kV Upper limit of laboratory test set.
H.V.
SUPPLY
±
V
D
IN
DUT
C
D
R
1
IEC 1000-4-2: R
1
50 to 100M R
D
CHARGE
SWITCH
DISCHARGE
SWITCH
MIL STD 3015.7: R
1
1 to 10M
FIGURE 1. ELECTROSTATIC DISCHARGE TEST
TABLE 1. ESD TEST CONDITIONS 248
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TVS Diode Arrays
SCR Diode Array for ESD and Transient Overvoltage Protection
SP724
FIGURE 2. LOW CURRENT SCR FORWARD VOLTAGE DROP
CURVE
FIGURE 3. HIGH CURRENT SCR FORWARD VOLTAGE DROP
CURVE
600
800
1000
1200
FORWARD SCR VOLTAGE DROP (mV)
200
160
120
80
40
0
FORW
ARD SCR CURRENT (mA)
T
A
= 25
o
C
SINGLE PULSE
5
4
3
2
1
0
FOR
W
ARD SCR CURRENT (A)
T
A
= 25
o
C
SINGLE PULSE
0
1
2
3
FORWARD SCR VOLTAGE DROP (V)
EQUIV. SAT. ON
THRESHOLD ~ 1.1V
+V
CC
INPUT
DRIVERS
SP724 INPUT PROTECTION CIRCUIT (1 OF 4 SHOWN)
OR
SIGNAL
SOURCES
IN 1, 3, 4 AND 6
SP724
V-
TO +V
CC
LINEAR OR
DIGITAL IC
INTERFACE
V+
+V
CC
0.01
µ
F
FIGURE 4. TYPICAL APPLICATION OF THE SP724 AS AN INPUT CLAMP FOR OVER-VOLTAGE, GREATER THAN 1V
BE
ABOVE V+ OR
LESS THAN -1V
BE
BELOW V- 249
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5
TVS DIODE ARRA
YS
TVS Diode Arrays
SP724
SCR Diode Array for ESD and Transient Overvoltage Protection
Peak Transient Current Capability for Long Duration Surges
The peak transient current capability is inversely proportional to the width
of the current pulse. Testing was done to fully evaluate the SP724s
ability to withstand long duration current pulses using the circuit of
Figure 5. Figure 6 shows the point of overstress as defined by increased
leakage in excess of the data sheet published limits. The safe operating
range of the transient peak current should be limited to no more than
75% of the measured overstress level for any given pulse width as
shown in the curve of Figure 6.
The test circuit of Figure 5 is shown with a positive pulse input. For a
negative pulse input, the (-) current pulse input goes to an SP724 IN
input pin and the (+) current pulse input goes to the SP724 V- pin. The
V+ to V- supply of the SP724 must be allowed to float. (i.e., It is not tied
to the ground reference of the current pulse generator.)
Note that two input pins of the SP724 may be paralleled to improve
current (and ESD) capability. The sustained peak current capability is
increased to nearly twice that of a single pin.
FIGURE 5. TYPICAL SP724 P