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EIA/JEDEC STANDARD EIA/JEDEC
STANDARD
STUB SERIES TERMINATED
LOGIC FOR 2.5 VOLTS (SSTL_2)
EIA/JESD8-9
SEPTEMBER 1998
ELECTRONIC INDUSTRIES ALLIANCE
JEDEC Solid State Technology Division


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JEDEC Standard No. 8-9
-i-
STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2)
A 2.5V Supply Voltage Based Interface Standard for Digital Integrated Circuits
CONTENTS
Page
1
Scope
1
1.1 Standard Structure
1
1.2 Rationale and assumptions
1
2
Supply voltage
2
2.1 Supply voltage levels
3
2.2 Input parametric
3
2.3 AC test conditions
4
3
SSTL_2 output buffers
5
3.1 Overview
5
3.2 SSTL_2 Class I output buffers
7
3.2.1 Push-pull output buffer for symmetrically single parallel terminated loads with
series resistor (VTT=0.5xVDDQ).
7
3.2.2 SSTL_2 Class I output ac test conditions
8
3.3 SSTL_2 Class II output buffers
9
3.3.1 Push-pull output buffer for symmetrically double parallel terminated loads with
series resistor (VTT=0.5xVDDQ).
9
3.3.2 SSTL_2 Class II output ac test conditions
10
4
Other applications
10
4.1 Push-pull output buffer for unterminated loads
10
4.2 Push-pull output buffer for symmetrically single parallel terminated loads
(VTT=0.5xVDDQ).
11
4.3 Push-pull output buffer for externally source series terminated loads
12
4.4 Push-pull output buffer for symmetrically double parallel terminated loads
(VTT=0.5xVDDQ).
13
Figures
1 SSTL_2 Input voltage levels
2
2 AC Input test signal wave form
4
3 Typical output buffer (driver) environment
5
4 Example of SSTL_2, Class I, symmetrically single parallel terminated output load,
and series resistor
7
5 Example of SSTL_2, Class II, symmetrically double parallel terminated output load
with series resistor
9 JEDEC Standard No. 8-9
-ii-
STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2)
A 2.5V Supply Voltage Based Interface Standard for Digital Integrated Circuits
CONTENTS (concluded)
Page
6 Example of SSTL_2 unterminated output load
11
7 Example of SSTL_2, Class I or Class II, buffer with symmetrically single parallel
terminated output loads
11
8 Example of SSTL_2, Class I or Class II, Externally Source Series terminated output
load
12
9 Example of SSTL_2, Class I, buffer with symmetrically double parallel terminated
output load
13
Tables
1 Supply voltage levels
3
2a Input dc logic levels
3
2b Input ac logic levels
3
3 AC input test conditions
4
4 Examples of how the limits of SSTL_2 circuit voltages depending on VDDQ
6
5a Output dc current drives
7
5b AC test conditions
8
6 Output dc current drive
9
7 AC test conditions
10 JEDEC Standard No. 8-9
Page 1
STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2)
A 2.5V Supply Voltage Based Interface Standard for Digital Integrated Circuits
(From JEDEC Council ballot JCB-97-80, formulated under the cognizance of the JC-16
Committee on Electrical Interface and power Supply Standards for Electronic Components.)
1 Scope
This standard defines the input, output specifications and ac test conditions for devices that are
designed to operate in the SSTL_2 logic switching range, nominally 0V to 2.5V. The standard
may be applied to ICs operating with separate VDD and VDDQ supply voltages. In many cases
VDD and VDDQ will have the same voltage level. The VDD value is not specified in this
standard other than that VDDQ value may not exceed that of VDD.
1.1 Standard structure
The standard is defined in three clauses:
The first clause defines pertinent supply voltage requirements common to all compliant ICs.
The second clause defines the minimum dc and ac input parametric requirements and ac test
conditions for inputs on compliant devices.
The third clause specifies the minimum required output characteristics of, and ac test conditions
for, compliant outputs targeted for various application environments. The output specifications
are divided into two classes, Class I and Class II, which are distinguished by drive requirements
and application.
A given IC need not be equipped with both classes of output drivers, but each must support at
least one to claim SSTL_2 output compliance.
The full input reference level (VREF) range specified is required on each IC in order to allow any
SSTL_2 IC to receive signals from any SSTL_2 output driver.
1.2 Rationale and assumptions
The SSTL_2 standard has been developed particularly with the objective of providing a relatively
simple upgrade path from MOS push-pull interface designs. The standard is particularly intended
to improve operation in situations where busses must be isolated from relatively large stubs.
External resistors provide this isolation and also reduce the on-chip power dissipation of the
drivers. Busses may be terminated by resistors to an external termination voltage. JEDEC Standard No. 8-9
Page 2
1 Scope (contd)
1.2 Rationale and assumptions (contd)
Actual selection of the resistor values is a system design decision and beyond the scope of this
standard. However in order to provide a basis, the driver characteristics will be derived in terms
of a typical 50 Ohms environment.
While driver characteristics are derived from a 50 Ohm environment, this standard will work for
other impedance levels. The system designer will be able to vary impedance levels, termination
resistors and supply voltage and be able to calculate the effect on system voltage margins. This is
accomplished precisely because drivers and receivers are specified independently of each other.
The standard defines a reference voltage VREF which is used at the receivers as well as a voltage
VTT to which termination resistors are connected. In typical applications VTT tracks as a ratio
of VDDQ. In turn VREF will be given the value of VTT. In some standards this ratio equals 0.5.
2 Supply voltage and logic input levels
The standard defines both ac and dc input signal values. Making this distinction is important for
the design of high gain, differential, receivers that are required. The ac values are chosen to
indicate the levels at which the receiver must meet its timing specifications. The dc values are
chosen such that the final logic state is u