Design Guide for Xilinx FPGA Power Management Systems
1 Introduction
Field Programmable Gate Arrays (FPGAs) are a class of programmable logic devices based on an array of logic cells surrounded by a periphery of input/output cells. These IC's can be programmed in the field after manufacture in order to implement specific design functions. The advanced technologies and smaller geometries used to fabricate the devices require increasingly lower supply voltages for the core voltage (typically 3.3, 2.5, 1.8, 1.5 and 1.2V). While the core supply voltage is decreasing, these devices must continue to support both newer and legacy interfaces, potentially requiring an I/O supply voltage which is different from the core voltage. Typical Vccio voltages range from 1.2V up to 3.6V. Legacy applications may require a 5V I/O supply. ST Microelectronics supports a complete power management solution for low and mixed-voltage FPGAs. This design guide serves to address the voltage and current requirements, including voltage sequencing, ramping, and current limiting. A list of regulators matching the minimum power supply requirement for Xilinx FPGA families is also included. The power requirements listed here are based on the most current information available. Designers should consult Xilinx's application literature for the up to date information. 2 Xilinx FPGA Requirements
2.1 Voltage Levels Xilinx FPGAs require a supply voltage of 3.3, 2.5, 1.8, 1.5 and 1.2V for the core, depending on the specific family of FPGAs. The I/O voltage requirement depends on which I/O standards the FPGA is supporting. These voltages can range from 3.3V to 1.2V. The Virtex-4TM, Virtex-IITM, Virtex-IITM Pro and the Spartan-3TM also require an auxiliary voltage. The Xilinx core, auxiliary and I/O voltage requirements for each family are listed in the table below: Xilinx FPGA Family Virtex-4TM Virtex-II ProTM Virtex-IITM Virtex-E/EMTM Spartan-3TM Spartan-3LTM Spartan-3ETM Spartan-IIETM Spartan-IITM Core Voltage 1.2V 1.5V 1.5V 1.8V 1.2V 1.2V 1.2V 1.8V 2.5V Auxiliary Voltage 2.5V 2.5V 3.3V N/A 2.5V 2.5V 2.5V N/A N/A I/O Voltage 1.2V to 3.3V 1.5V to 3.3V 1.5V to 3.3V 1.2V to 3.3V 1.2V to 3.3V 1.2V to 3.3V 1.2V to 3.3V 1.2V to 3.3V 1.5V to 3.3V Version 2.0 ­ September 05 1/11 Design Guide for Xilinx FPGA Power Management Systems 2.2 Power-On Requirements At power-up, a minimum level of core supply current must be provided to the Xilinx FPGAs in order to properly power-up and configure. In addition, the core voltage Vccint ramp time must be within a certain range, as specified in the datasheet for each family. The power supplies must also rise monotonically with a voltage droop less than 10mV/ms. The power-up current and ramp time specifications for each family are as follows: Xilinx FPGA Family Virtex-4TM Virtex-II ProTM Virtex-IITM Virtex-ETM Spartan-IITM Spartan-IIETM Spartan-3TM Spartan-3LTM Spartan-3ETM Min Power-Up Current (mA) Core Aux I/O Up to 850 500 N/A Up to 2200 250 100 Up to 1100 100 100 Up to 2000 100 250 ­ 2000 N/A 300 ­ 2000 N/A 55 ­ 340 N/A N/A 55 ­ 340 N/A N/A 55 ­ 340 N/A N/A Ramp Time Specification 200µs < Tccpo < 50ms 200µs < Tccpo < 50ms 1ms < Tccpo < 50ms 2ms < Tccpo < 50ms Tccpo < 50ms 2ms < Tccpo < 50ms no limit