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A GaN HEMT Power Amplifier with Variable Gate Bias for Envelope and Phase Signals
Abstract
- This paper describes the design, simulation and
measurement of a GaN power amplifier suitable for envelope
and phase signal combination. The low-frequency envelope
signal is used to vary the gate (bias) voltage of the device,
resulting in a pulse width modulated drain voltage, while
modulation of supply voltage or current is avoided. The test
circuit is implemented using a discrete GaN HEMT power
amplifier and discrete surface-mount passive components
assembled on a PCB. Measurements showed a maximum drain
efficiency of 59% at 360 MHz, at an output power of 29 dBm.
The output power as a function of the gate bias voltage varied
between 3 and 29 dBm, with the drain efficiency varying
between 6 and 59%.
I. I
NTRODUCTION
Some of the challenges of modern telecommunication
systems are power consumption and performance of the
transmitter. Communication systems develop towards
higher frequencies, larger bandwidths, higher transmit
output power and larger peak-to-average ratios, while user
handsets and base stations at the same time are operating for
multiple standards. Thus, the transmitter linearity
requirements become more stringent. Due to increased
performance requirements in both handsets and base
stations, power consumption is an issue for both
components, as cooling is an increasingly costly factor of
base stations and battery lifetime is a well-known factor of
handsets.
The power amplifier is a critical component in the
transmitter; A typical class-A solution will provide linearity
but will lead to high power consumption in order to meet
performance requirements. Therefore, many architectural
solutions have been investigated and implemented, such as
Envelope Elimination and Restoration (EER), Envelope
Tracking (ET), Linear Amplification with Non-Linear
Components (LINC), etc [1-5]. On the circuit design level,
an increased interest in switch-mode power amplifiers (PA)
has been shown, also at radio frequencies [3, 6, 7].
In this paper we present a power amplifier architecture
suitable for a transmitter using separated envelope (low-
frequency) and phase (high-frequency) signals (see Fig. 1).
The PA is switch-mode, and both the low- and high-
frequency signal operate on the gate of the GaN HEMT; The
envelope drive signal controls the gate bias signal, which is
a low level signal and so there is no need for a switch mode
amplifier as is required for systems using drain voltage
modulation, and no modulation of the supply voltage or
current occurs.
It is well known that modern modulation schemes such
as W-CDMA and OFDM require very linear amplification.
Unfortunately, this amplifier structure is designed for
efficiency and is far from linear, so some form of
linearization will be required before the signal splitter stage.
Digital Predistortion (DPD) [9] would be a potential
candidate for this as it can handle wide bandwidths and
memory effects can also be included.
The signal separator that splits the envelope and phase
components is best done using envelope tracking techniques
to avoid the spectrum expansion on the phase modulated
drive signal. Overdriving the driver amplifier feeding the PA
can remove the modulation on this waveform.
The transmitter may be implemented by having the
predistorter, modulator and limiter on a single chip, driving
the power amplifier.
Because of practical limitations, and having the goal of
testing this PA concept in mind, the operating frequency of
the power amplifier is designed to be 400 MHz. This is
done by choosing suitable discrete component values for the
input and output tuning network. The discrete GaN HEMT
device is chosen in order to achieve a high output power and
a high efficiency in switch-mode. The full amplifier
including matching networks is implemented using surface
mount components on a standard FR4 PCB, with double
sided copper layers.
In section 2 of this paper the amplifier design is
described, and in section 3 simulation and measurement
results are presented. Conclusions are drawn in section 4.
Ellie Cijvat
1
, Kevin Tom
2
, Mike Faulkner
2
and Henrik Sjöland
1
A GaN HEMT Power Amplifier with Variable
Gate Bias for Envelope and Phase Signals
1
Dept. of Electrical and Information Technology, Lund University, Sweden
P.O. Box 118, SE-221 00 Lund, Sweden
e-mail:
{ellie.cijvat, henrik.sjoland} @eit.lth.se
2
Centre for Telecommunications and Micro-Electronics (CTME), Victoria University, Australia
P.O. Box 14428 MCMC, Melbourne 8001, Australia
e-mail:
kevint@camsav.vu.edu.au
, mf@ee.vu.edu.au
Fig. 1. Transmitter architecture.
limiter
DPD
mod
envelope
phase
PA
Copyright © 2007 IEEE. Reprinted from 2007 IEEE NORCHIP CONFERENCE
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you agree to all provisions of the copyright laws protecting it. I. C
IRCUIT
D
ESIGN
As mentioned in the Introduction, the envelope (low-
frequency) signal is used to effectively change the bias level
at the gate of the device. The phase (limited, high-frequency)
signal thus causes the transistor to be switched on for a
shorter or longer length of time, as illustrated in Fig. 2.
This results in a pulse-width modulated signal at the drain
of the device. This signal is then filtered by the output
tuning network, giving a variation in output power, as
desired.
The PA is shown in Fig. 3. The output tuning network
provides filtering of the square-wave drain voltage signal
and performs impedance transformation from the load
impedance to the drain of the device. The networks were
optimized and fine-tuned in order to accomodate a range of
pulse widths by simulations using the harmonic balance
simulation in ADS.
(a)
(b)
The inductor at the drain of the device is implemented
through a transmission line on the PCB, giving an
inductance of approximately 0.6 nH at 400 MHz. All other
passive components are surface mounted on the PCB.
The device is a Cree CGH40010 discrete GaN HEMT
device suitable for high output power (typically 13W at P
-
3dB
) and high efficiency (60% at P
-3dB
). The threshold voltage
is typically -2.5 V, and the specified supply voltage is 28 V
[8]. In our measurement setup we limited the supply voltage
to 10 V, due to practical considerations.
The original modulated baseband signal is restored at RF
at the output of the PA, as the variable gate bias level
combines with the constant-envelope high-frequency signal.
The output network to some extent provides filtering of the
desired output frequency band. It must be noted that the
characteristic from the low-frequency signal to the output is
non-linear; It is assumed that pre-distortion [9] or feedback
[10] is used.
I. R
ESULTS
A. Simulation results
The power amplifier was simulated using the harmonic
balance simulation in ADS. The transmission line and other
PCB traces were taken into account as well. Simulations
showed a maximum drain efficiency of 78% at 400 MHz, at
an output power of 34.5 dBm, and a maximum output
power of 38.5 dBm at 450 MHz (see Fig. 4) for a supply
voltage of 18 V, V
bias
of -3 V and the amplitude of the input
voltage at 10 V.
.
For a variation of V
bias
from -1.5 to -7 V, the output
power varies from 35.7 to 8.4 dBm, while the efficiency
varies from 86.4 to 8.4%.
A supply voltage of V
dd
= 10 V will according to
simulations give a drop in output power of approximately 5
dB while maintaining the same level of efficiency.
B. Measurement results
The circuit was assembled on the PCB (see Fig. 5), and a
GaN PA, 400MHz, Vdd=18V, Vbias=-3
0
5
10
15
20
25
30
35
40
45
250
300
350
400
450
500
550
600
650
frequency (MHz)
Output power (dBm)
0
10
20
30
40
50
60
70
80
90
Efficiency (%)
Output power
Efficiency
phase
envelope
Fig. 4. Simulation results for V
d d
= 18 V, V
in,peak
= 10 V and V
bias
= -3 V.
Fig. 2. Operating principle of the power amplifier. The difference v
between V
bias
and V
th
varies, depending on V
bias
, and the resulting
pulse width modulated drain voltage is illustrated for two cases.
V
1
V
2
v
drain,1
v
drain,2
v
in
Fig. 3. Power amplifier schematic, (a). Block diagram, (b).
Implementation.