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Click to edit Master Title Live At Power Up
2005 System Design Needs © 2005 Actel Confidential and Proprietary
3
June 2005
Live at Power-Up
Live-at-Power-Up
Designer Perspective
System Designs are more efficient and simpler
if programmable logic is live immediately on
power-up
System component initialization and control during power-up
Perform time critical tasks before processor wakes up
Setup and configure memory blocks (e.g. microcontroller
address bus decoding)
Provide clocks (through PLL circuitry) immediately to the rest
of the system
Manage bus activity
Reduce component count and system power consumption © 2005 Actel Confidential and Proprietary
4
June 2005
Live at Power-Up
Applications Requiring Short
Initialization Time
Industrial/Medical
Critical operation that does not allow reconfiguration time after
power-up or power glitches
Life assistance equipment
Battery management
Consumer
Applications with frequent power-up/down
Reduced power consumption and time to initialize
Military
Missile control
Automotive
Engine startup control
Obsolete ASICs
Requiring FPGAs that are live-at-power-up for compatibility System Power-Up Classification © 2005 Actel Confidential and Proprietary
6
June 2005
Live at Power-Up
Programmable Logic Technologies
SRAM
Hybrid FPGAs/CPLDs SRAM
fabric loaded from NVM on chip
SRAM
SRAM FPGA with boot
(PROM or MCU)
EEPROM
SPLD/CPLDs EEPROM
or
SRAM
FPGA
PROM
MCU +
NVM
Flash/Antifuse
NVM FPGAs
NVM
FPGA
NVM
SRAM
FPGA/CPLD
EEPROM
SPLD/CPLD © 2005 Actel Confidential and Proprietary
7
June 2005
Live at Power-Up
System Power-Up Stages
0
100µs
10ms
500ms
System
Voltage
1
1s+
Power
Management,
System Critical
Tasks, Clocks
System configuration, supervisory
(Bootable devices)
Power Up
Voltage
Vcc -
Vcc Reg
System level
devices,
Processors
Peripheral
components
System Initialized
Power On
1ms
Vcc +
Voltage
Trigger
Point
50µs
Notes
1.
Times are not to scale and are an estimate for a generic system with
one critical supply voltage
Time after Power-On
1 © 2005 Actel Confidential and Proprietary
8
June 2005
Live at Power-Up
Power-Up Device Classification
Functionality
Class
Description
Level
Processors initialization
(boot) after environment
setup. SRAM Based FPGAs
loaded from boot prom.
Periphery component set-up
least critical to system
operation. SRAM FPGAs
loaded from micro
controller/processor.
System configuration and
initialization, supervisory
and monitoring tasks.
Setup memories and
interfaces for
microprocessors access.
Hybrid CPLDs/FPGAs
Regulates critical system
tasks to initialize
environment. Provides
clocks and critical logic
functions during power ramp
up and until system is
powered up
Non-volatile FPGAs
(Antifuse and Flash), some
CPLDs and ASICs
Live After system initialized
Live After power up
Live At Power On
2
1
0
Power Up
Power On
System Initialized
Actel FPGAs support Level 0 - Live at power-up
SRAM FPGAs support only Level 2 Live after system initialized
Hybrid FPGAs support Level 1 or Level 2 Live after power-up
or after system initialized © 2005 Actel Confidential and Proprietary
9
June 2005
Live at Power-Up
Programmable Logic Devices
Power Up timing
0
70 µs
1
22V10
SPLD
(EEPROM)
0
70 µs
1
MAX7000
CPLD
(EEPROM)
0
50µs
Flash ProASIC3
Actel FPGA
0
60µs
Antifuse
Actel FPGA
>200ms
3
>200ms
>1 ms
2
200 µs
Power-Up
Time
(est./test)
Altera FPGA
Xilinx FPGA
Lattice FPGA
Hybrid CPLD
2
Spartan3 XC3S200
2
Cyclone, Cyclone II
1
LatticeXP
1
MAX II
CoolRunner II
Live At
Power-Up
(LAPU)
Classification
Family
Power On
Power Up
100
µs
System
Initialized
10ms
Notes
1.
Estimated time
2.
Based on the company statement
3.
Best Case conditions taken from datasheet
4.
FPGA core voltage ramp up 100
µ
s © 2005 Actel Confidential and Proprietary
10
June 2005
Live at Power-Up
Live at Power-Up
NVM vs. SRAM FPGA
System Power
Output
System Power
Output
Configuration
Clock
Spartan 3
XC3S200
Axcelerator
AX250
FPGA Output Active
Immediately after voltage trigger
Voltage trigger
Vcc min
FPGA Output Active
>200ms
SRAM-based FPGAs
have to be configured
on every power up
cycle
Meet Level 2, live after
system initialized
NVM devices meet
Level 0 live at power-
up
x4000 faster than nearest
competitor © 2005 Actel Confidential and Proprietary
11
June 2005
Live at Power-Up
Live at Power-Up
NVM vs. SRAM (Hybrid) FPGA
FPGA Output Active
>200
µs
FPGA Output Active
Immediately after voltage trigger
Voltage trigger
Vcc min
System Power
Output
System Power
Output
Configuration
Clock
Max II
EPM1270
ProASIC3
A3PE600
Hybrid FPGAs have to
be configured after
every power up cycle
Typically meet Level 1,
live after power-up
Flash FPGAs meet
Level 0 live at power-
up
x20 faster typically than
nearest competitor SRAM FPGA and NVM FPGA
System Functionality © 2005 Actel Confidential and Proprietary
13
June 2005
Live at Power-Up
Live at Power Up
SRAM FPGA Example 1
System using SRAM FPGA loaded from
external Flash
Power Up Sequence
1.
Power On (applied)
2.
Regulate power, clock
3.
Apply Reset and provide
clocks to devices
4.
SPLD Address Memory
for MCU
5.
Power Up (stable)
6.
Components initialized
7.
MCU wakes up and starts
initializing
8.
MCU operational
9.
FPGA configuration
loaded from MCU
10.
FPGA operational
Live At power up
(Level 0)
Live After power up
(Level 1)
Live After system
initialized (Level 2)
MCU
Flash
Memory
SRAM
FPGA
Address/data
Decode SPLD
Xtal
Osc.
Reset
Controller
(CPLD)
Clock
Generation
PLL/Dividers
Address/Data
Address/Data
Address/Data
Config.
ASSP
Time
0 ns
100
µs
>200 ms © 2005 Actel Confidential and Proprietary
14
June 2005
Live at Power-Up
Live at Power Up
SRAM FPGA Example 2
System using SRAM FPGA loaded from Flash
MCU
Time
0 ns
(Flash)
MCU
Config.
Flash
SRAM
FPGA
Xtal
Osc.
Reset
Controller
(CPLD)
Clock
Generation
PLL/Dividers
Config.
ASSP
Power Up Sequence
1.
Power On (applied)
2.
Regulate power, clock
3.
Apply Reset and provide
clocks to devices
4.
Power Up (stable)
5.
Components initialized
6.
MCU wakes up and starts
initializing
7.
MCU operational
8.
FPGA configuration
loaded from MCU
9.
FPGA operational
100
µs
Live At power up
(Level 0)
Live After power up
(Level 1)
Live After system
initialized (Level 2)
>200 ms © 2005 Actel Confidential and Proprietary
15
June 2005
Live at Power-Up
Live at Power Up
SRAM FPGA Example 3
System using SRAM FPGA loaded from
external boot PROM
MCU may be Flash based or loaded from external Flash
MCU
Flash
Memory
SRAM
FPGA
Address/data
Decode SPLD
PROM
Xtal
Osc.
Reset
Controller
(CPLD)
Clock
Generation
PLL/Dividers
ASSP
Live At power up
(Level 0)
Live After power up
(Level 1)
Live After system
initialized (Level 2)
Time
0 ns
Power Up Sequence
1.
Power On (applied)
2.
Regulate power, clock
3.
Apply Reset and provide
clocks to devices
4.
SPLD initializes Memory
for MCU
5.
Power Up
6.
Components initialized
7.
MCU loads from internal
Flash/FPGA uploads
from configuration
PROM
8.
MCU and FPGA
operational
100
µs
>200 ms © 2005 Actel Confidential and Proprietary
16
June 2005
Live at Power-Up
Live at Power Up
Hybrid FPGA Example 4
System using Hybrid FPGA
Configuration loaded from on-chip NVM after power-up
Reset
Controller
(CPLD)
Clock
Generation
PLL/Dividers
Xtal
Osc.
Time
0 ns
Power Up Sequence
1.
Power On (applied)
2.
Regulate power, clock
3.
Apply Reset and provide
clocks to devices
4.
SPLD initializes Memory
for MCU
5.
Power Up
6.
Components initialized
7.
FPGA Operational
8.
MCU loads from internal
Flash
9.
MCU operational
100
µs
MCU
ASSP
Hybrid
FPGA
Live At power up
(Level 0)
Live After power up
(Level 1)
Live After system
initialized (Level 2)
200
µs - 1.5 ms © 2005 Actel Confidential and Proprietary
17
June 2005
Live at Power-Up
Live at Power Up
Actel NVM FPGA Case
Circuit showing design implementation using
Actel Flash FPGA
Power Up Sequence
1.
Power On (applied)
2.
Regulate power, clock
3.
Actel FPGA is Live, I/Os
active
FPGA applies Reset
and
provides Clocks to
devices
4.
FPGA initializes
memory
5.
Power Up (stable)
6.
Component