closed-loop combination with op amps to drive
co-axial cables and capacitive or other high-current loads
Features and characteristics of these buffers are summa-
rized in Table I All are active trimmed for low unadjusted
output offset voltage and uniform performance Good ther-
mal coupling between dice is achieved by hybrid thick-film
construction on ceramic substrates
Part I analyzes the AC and DC equivalent circuits
Part II is a comprehensive guide to applications techniques
and shows how to get optimum performance under a variety
of circumstances
Finally Part III illustrates these techniques in some specific
applications including drivers sample-and-hold amplifiers
and active filters
I CIRCUIT DESCRIPTIONS
General
The three buffer amplifiers share a similar class AB emitter-
follower output stage as shown in
Figure 1 The symmetrical
class AB amplifier output provides current sourcing or sink-
ing and relatively constant low impedance to the load during
positive and negative output swing The input stage of the
LH0002 consists of a complementary bipolar emitter-follow-
er The LH0033 and LH0063 employ junction FETs config-
ured as source-followers thereby achieving several orders
of magnitude improvement in DC input resistance over the
LH0002 In each case the output stage collectors are un-
committed to allow the use of current limiting resistors in
series with either or both output collectors
LH0002 Low Frequency Operation
The LH0002 circuit shown in
Figure 2 is a compound emit-
ter-follower with small-signal current gain of approximately
40 000 (product of first and second stage betas)
TL H 8725 1
FIGURE 1 LH0002 Simplified Output Stage
TL H 8725 2
FIGURE 2 LH0002 Schematic Diagram
TABLE I Buffer Amplifier Typical Characteristics
Parameter
Conditions
LH0002
LH0033
LH0063
Units
DC Output Current Continuous
g
100
g
100
g
250
mA
Peak Output Current
g
200
g
250
g
500
mA
Slew Rate
R
L
e
1 kX R
S
e
50X
200
1500
6000
V ms
Bandwidth 3 dB
50
100
180
MHz
Voltage Gain
V
IN
e
1V
1 kHz R
L
e
1k
0 97
0 98
0 98
V V
Output Offset Voltage
T
C
e
25 C R
S
e
100 kX
g
10
g
5
g
10
mV
(R
S
e
300X for LH0002)
Input Bias Current
T
C
e
25 C
6 mA
50 pA
100 pA
Output Resistance
6
6
1
X
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A Operation is symmetrical and the circuit may be analyzed
by considering only the upper or the lower half of the circuit
as redrawn in
Figure 3 Input stage operating current is de-
termined by R1 in conjunction with supply and input volt-
ages For V
IN
e
0 and V
S
e
g
15V first stage quiescent
current is typically
I
C
e
V
S
b
V
BE
b
V
IN
R1
e
15
b
0 63
b
0
5000X
e
2 88 mA
(1)
The normal production variation of I
C
is
g
5%
The emitter-base junction of the first and second stages
appear in series between input and output terminals there-
fore the output offset voltage for V
IN
e
0 is the difference in
base-emitter junction voltages of a PNP and an NPN tran-
sistor This is true for both upper and lower halves of the
circuit so there is no conflict between the two circuit halves
Output stage quiescent current will equal that of the input
stage if the transistors are matched and at equal tempera-
tures This establishes a class AB bias in the output stage
so there is no class B crossover distortion in the output
Resistors R3 and R4 inserted in the output emitter circuits
minimize the effect of unmatched upper and lower circuit
halves and limit the potential for thermal runaway due to
input and output stage temperature differences There is no
thermal runaway if operation is confined within data sheet
limits
Maximum output current is dependent on the supply volt-
age R1 Q3 current gain and the output voltage Maximum
current is available when V
IN
rises sufficiently above V
OUT
that Q1 is cut off Under this condition the 5k resistor sup-
plies base current to Q3 and the maximum output current
is
I
O(MAX)
e
V
S
b
V
BE3
b
I
O
R3
b
V
O
R1 b
3
e
V
S
b
V
BE3
R1 b
3
a
R3
a
R
L
j V
S
b
0 7
30
a
R
L
(2)
where b
3
j
200
If V
S
e
g
15V the LH0002 can theoretically deliver about
500 mA peak into a shorted load (in practice only 400 mA
peak can be realized for the current density in the output
transistors limits the beta to about 150) or 180 mA peak into
50X Current limiting may be employed for short circuit pro-
tection (see section on Current Limiting)
The voltage gain of the LH0002 is slightly less than unity
and is a function of load as with any emitter-follower It is
dominated by the finite output resistance of the output
stage Hence the gain analysis for all three buffers can uti-
lize the hybrid
q
model as shown in
Figure 4 Note that r
e3
is the emitter dynamic resistance of Q3 and is load-current
dependent The gain expression written as a function of
load resistance and input voltage is
A
v
j
R
L
R
L
a
R3
a
r
e3
e
R
L
R3
a
R
L

1
a
0 026
V
O
a
0 003R
L
J
(3)
e
R
L
R3
a
R
L

1
a
0 026
V
IN
J
VIN
l
0 1V
Voltage gain could range from 0 996 for R
L
e
1 kX to 0 978
for R
L
e
100X at 10V input In contrast the same loads
would yield gains of 0 973 to 0 956 respectively for an in-
put of 1V because r
e3
would be somewhat larger
Because of the inherent current-mode feedback initial off-
set error is typically 10 mV with a finite (300X) series input
resistance Even with unsymmetrical supplies V
OS
increas-
es only an additional 3 mV per volt of supply differential
Usually this error component may be ignored as it is rela-
tively small compared to the large-signal error predicted by
equation (3) when driving heavy loads
TL H 8725 3
FIGURE 3 LH0002 Half Circuit
TL H 8725 4
Where r
e3 e
0 026 I
O
FIGURE 4 Equivalent Model of LH0002
2 LH0002 High Frequency Operation
The high frequency response is limited primarily by internal
circuit capacitances most significant are the junction capac-
itances shown in
Figure 5
Since the base-emitter junction capacitances of emitter-fol-
lowers see little effective junction voltage change they may
be neglected in the following first-order analysis For the
transistors used we may also assume that the transistor de-
lay and transit time effects are over-shadowed by the RC
effect We can then simplify the half-circuit to that of
Figure
6 a single transistor emitter-follower plus an equivalent load
reflected from the output stage
Evaluation of the transfer function of equation (4) as derived
from
Figure 6b indicates that the input pole dominates for
finite source resistance
e
o
(s)
e
in
(s)
e

R2
R2
a
R
s
J 
b
3
R
L
b
3
R
L
a
r
out
J
1
a
s (R2
ll
R
s
) C
CB1
1
a
s (r
out
ll
b
3
R
L
) C
CB3
(4)
j
A
V
(low frequency)
(1
a
s R
s
C
CB1
) (1
a
s r
e1
C
CB3
)
To illustrate for R
s
e
300X the primary pole is predicted to
occur at about 60 MHz a close correlation to the real value
while the output pole is well beyond 1 GHz The implication
of this analysis is quite significant
the fundamental band-
width of the LH0002 is a function of the input source resist-
ance within a reasonable range of 50X to 300X For the
case of R
S
e
50X the resulting bandwidth is well above
100 MHz
TL H 8725 5
FIGURE 5 LH0002 High Frequency Circuit
C
CB1 e
C
CB1 a
C
CB2
j
9 pF
C
CB3
j
6 pF
TL H 8725 6
TL H 8725 7
Where r
OUT
j

r
e1 a
R
S
b
1
J
ll
R1
R2
e
b
1
(r
e1 a
R1
ll
b
3
R
L
)
FIGURE 6a LH0002 Simplified Mirror-Half Input Stage
FIGURE 6b Hybrid
q
Model
3 TL H 8725 8
a Negative Pulse Response
TL H 8725 9
b Positive Pulse Response
TL H 8725 10
c Negative Pulse Response
TL H 8725 11
d Positive Pulse Response
FIGURE 7 LH0002 Pulse Response
LH0002 Large Signal Pulse Response
Figure 7 shows the typical large signal pulse response of
the LH0002
LH0033 Low Frequency Operation
The LH0033 circuit can be described in simplified form
Fig-
ure 8 as a source-follower plus a balanced emitter-follower
The complete circuit is shown in
Figure 9
TL H 8725 12
FIGURE 8 LH0033 Simplified Circuit
When Q1 and Q2 are well matched offset voltage and drift
will be low because the gate-source voltage of Q2 V
GS2
is
set j2 V
BE
thus forcing V
GS1
e
V
GS2
due to the matching
when operating at equal currents However as load current
is drawn from the output Q1 and Q2 will drift at slightly
different rates as I
D1
will no longer equal I
D2
by the differ-
ence in output stage base current Resistor R2 is trimmed to
establish the drain current of current-source transistor Q2 at
10 mA and R1 is trimmed for zero offset
TL H 8725 13
FIGURE 9 Complete LH0033 Schematic Diagram
4 The same current flowing through Q2 also flows through Q1
and R1 causing a gate-source voltage of approximately
1 6V The 10 mA flowing through R1 plus Q3s V
BE
of 0 6V
causes V
OUT
e
0 for V
IN
e
0 The output stage current is
established to be approximately equal to that of the input
stage by Q3 and Q4
Voltage gain of the LH0033 is the product of the 1st and
2nd stage gains taken independently The analysis of each
is shown in
Figure 10 We can write the total amplifier gain
expression as
A
V
e
1
1
a
2 R
L
a
167 b
5
R
L
a
0 26 V
IN
(5)
where b
5
j
200
Voltage gain is predicted to be 0 995 for a 1 kX load and
0 95 for a 50X load at 10V output
LH0033 High Frequency Operation
Low frequency performance is modified at high frequencies
by the increasing effect of transistor junction capacitance
Transistors Q3 Q4 and the output emitter-follower pair con-
tribute only minor incremental effect on the first-order high
frequency equivalent circuit so they may be omitted to yield
the simplified model appearing in
Figure 11 Modeling of
transistor Q1 reduces the circuit to that of
Figure 12
TL H 8725 14
TL H 8725 15
A
v1 e
R0
ll
b
5
R
L
R0
ll
b
5
R
L a
1 g
fs1 a
R1
e
1
1