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DC-DC Converter Application Manual


1
Note:
1. This datasheet is downloaded from the website of Murata Manufacturing co., ltd. Therefore, it s specifications are subject to change or our
products in it may be discontinued without advance notice. Please check with our sales representatives or product engineers before ordering.
2. This datasheet has only typical specifications because there is no space for detailed specifications. Therefore, please approve our product
specifications or transact the approval sheet for product specifications before ordering.

2006.10.2
MPDTH03060Y** Application
1
DC-DC Converter Application Manual

MPDTH03060Y
**

























NOMINAL SIZE = 25.27 mm x 15.75 mm























Standard Application




















Cin : Required 330µF, Capacitor

Co1 : Required 470µF, Low-ESR Electrolytic Capacitor


Co2 : Ceramic Capacitor for Optimum response, 200µF





10-A, 3.3-V Input Non-Isolated DDR/QDR
Memory Bus Termination Module
Features
VTT Bus Termination Output
(Output Track the System Vref)
10-A Output Current
3.3-V Input Voltage
DDR and QDR Compatible
Efficiencies up to 91 %
57 W/in
3
Power Density
On/Off Inhibit(for Vtt Standby)
Under-Voltage Lockout
Output Over-Current Protection
(Non-Latching, Auto-Reset) Operating Temp: -40 to +85

o
C Point-of-Load Alliance
Compatible
Description
The MPDTH03060Y are a series of ready-to-use
switching regulator modules from Murata
designed specifically for bus termination in DDR
and QDR memory applications. Operating 3.3-V
input, the module generates a VTT output that
will source or sink up to 10 A of current to
accurately track their Vref input. VTT is the
required bus termination supply voltage, and
Vref is the reference voltage for the memory and
chipset bus receiver comparators. Vref is usually
set to half the VDDQ power supply voltage.
The MPDTH03060Y employs an actively
switched synchronous rectifier output to provide
state-of-the-art stepdown switching conversion.
The products are small in size (25.4mm ×
15.75mm), and are an ideal choice where space,
performance, and high efficiency are desired,
along with the convenience of a ready-to-use
module.
Operating features include an on/off inhibit and
output over-current protection (source mode only).
The on/off inhibit feature allows the VTT bus to be
turned off to save power in a standby mode of
operation. To ensure tight
load regulation, an output remote sense is also
provided. Package options include both
throughhole and surface mount configurations.
Pin Configuration
Pin
Function
1 GND
2 Vin
3 Inhibit
4 No
Connect
5 Vo
Sense
6 VTT
7 GND
8 Vref
9 No
Connect
10 No
Connect
Open=ON
Short=OFF
RL
Vin
MPDTH03060Y
2
6
4
3
Cin:
330µF
1
8
Co2:
200µF
10
9
7
5
Vin
Inhibit
GND
Vo Sense
VTT
+
Co1:
470µF
V
DDQ

Vref
R2:
1k
R1:
1k
+


Note:
1. This datasheet is downloaded from the website of Murata Manufacturing co., ltd. Therefore, it s specifications are subject to change or our
products in it may be discontinued without advance notice. Please check with our sales representatives or product engineers before ordering.
2. This datasheet has only typical specifications because there is no space for detailed specifications. Therefore, please approve our product
specifications or transact the approval sheet for product specifications before ordering.

2006.10.2
MPDTH03060Y** Application
2








Ordering Information


Output Voltage (MPDTH03060 xx) Package Options (MPDTH03060x )


Code Voltage Code
Description
Y

0.55V-1.8V(Adjustable) AH
Horiz. T/H
AS
SMD(*1)


Notes

(1) Pb free (Sn-Ag-Cu) pin solder material.


Pin Description


10-A, 3.3-V Input Non-Isolated DDR/QDR
Memory Bus Termination Module
Vref:
The module senses the voltage at this input to regulate
the output voltage,
VTT
. The voltage at
Vref
is also
the reference voltage for the system bus receiver
comparators. It is normally set to precisely half the bus
Vref
8 driver supply voltage (VDDQ÷ 2), using a resistor
divider. The Thevenin impedance of the network driving the
Vref
pin should not exceed 500 . See the Typical DDR
Application Diagram in the Application Information
section for reference.

Vo Sense:
The sense input allows the regulation circuit to
compensate for voltage drop between the module and
the load. For optimal voltage accuracy
Vo Sense
should
be connected to
VTT
.

No Connect
: No connection.


Vin:
The positive input voltage power node to the module,
which is referenced to common
GND
.

VTT:
This is the regulated power output from the module with
respect to the
GND
node, and the tracking
termination supply for the application data and address buses. It
is precisely regulated to the voltage applied to the module's
Vref
input, and is active about 20 ms after a valid input source is
applied to the module.
Once active it will track the voltage applied at Vref.

GND:
This is the common ground connection for the
VIN
and
VTT
power connections. It is also the 0 VDC
reference for the control inputs.

Inhibit:
The Inhibit pin is an open-collector/drain negative logic
input that is referenced to
GND
. Applying a low-level
ground signal to this input turns off the output voltage,
VTT
.
Although the module is inhibited, a voltage, VDDQ
will be present at the output terminals, fed through the DDR
memory. When the Inhibit is active, the input current drawn by
the regulator is significantly reduced. If the Inhibit pin is left open
circuit, the module will
produce an output whenever a valid input source is applied. See
the Typical DDR Application Diagram in the
Application Information section for reference.



Note:
1. This datasheet is downloaded from the website of Murata Manufacturing co., ltd. Therefore, it s specifications are subject to change or our
products in it may be discontinued without advance notice. Please check with our sales representatives or product engineers before ordering.
2. This datasheet has only typical specifications because there is no space for detailed specifications. Therefore, please approve our product
specifications or transact the approval sheet for product specifications before ordering.

2006.10.2
MPDTH03060Y** Application
3






Environmental & Absolute Maximum Ratings
(Voltages are with respect to GND
)
Characteristics
Symbols
Conditions
Min
Typ
Max
Units
Control Input Voltage
Vref

-0.3
-
Vin+0.3
V
Operating Temperature Range
Ta
Over Vin Range
-40
(i)

-
85
o
C
Strage Temperature
Ts
-
-40

125
o
C
Solder Reflow Temperature
Treflow
Surface temperature of module body or pins


245
(ii)

o
C
Notes:

(i) For operation below 0
o
C the external capacitors must have stable characteristics. Use either a low ESR tantalum, Os-Con, or ceramic capacitor.
(ii) During reflow of SMD package version do not elevate peak temperature of the module, pins or internal components above the stated maximum


Electrical Specifications

(Unless otherwise stated, Ta =25
o
C, Vin =3.3 V, Vref =1.25 V, Cin =330µF, Co1 =470µF, Co2 =200µF, and Io =Iomax)





Characteristics
Symbols
Conditions
Min
Typ
Max
Units
Output Current
Io
Over Vref Range
0
-
±10
(1)

A
Input Voltage Range
Vin
Over Io Range
2.95
(2)

-
3.65
V
Tracking range for Vref
Vref

0.55
-
1.8
V
Tracking tolerance to Vref
|VTT-Vref|
Over line, load and temperature Io=0A
-10
-
10
mV
Efficiency

Io=8A
-
86
-
%
Vo Ripple (pk-pk)
Vr
20 MHz bandwidth
-
20
-
mVpp
Short Circuit Protection
Io trip
Reset, Followed by Auto-Recovery
-
20

A
Load transient response

15 A/µs load step, from 1. 5A to 1.5A





ttr
Recovery Time
-
30
-
µsec

Vtr
Vo Deviation
-
25
40
mV
Rising UVLO Threshold
UVLOr
Vin Increasing
-
2.45
2.8
V