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Computerised Dynamic Testing of Protective Relays: Development of Relay Test Bench for Testing of Overcurrent Relays
Computerised Dynamic Testing of Protective Relays: Development
of Relay Test Bench for Testing of Overcurrent Relays
A K Maitra, Member
A Rakshit, Member
S K Basu, Fellow
This paper reports a computerised dynamic relay test bench developed for testing of over current relays. This set is
capable of producing 3-phase transient current signals that correspond to the actual fault events in the power system.
Facilities are provided to generate fault transients either by simulating faults, using alternative transient program
(ATP) or by replaying the records of digital fault recorder (DFR). Facilities are also provided to generate harmonic
current signals through computer by software programming with user selectable magnitude and phase. This
approach offers improved testing facilities over existing system of relay testing.
Keywords : Computerised testing; Over current relays; Current amplifier design in linear mode
INTRODUCTION
Coordinated control and protection schemes have been deve-
loped in stages using analog electronic or digital hardware. This
new scheme replaces the traditional power system protection
scheme having physically segregated elements where each per-
forms its own specific function. This gradual development from
electromagnetic relays to digital one took place with a view to
satisfy the fundamental requirements more stringently.
Traditional practice for relay testing uses test set capable of
producing sinusoidal test signals in order to perform routine and
type test. In this arrangement a relay cannot be tested with
voltage and or current source having higher harmonic compo-
nents and decaying dc component.
The operating speed of modern power system protection has
improved significantly with the introduction of new analog and
digital relaying techniques
1
. In certain cases, fault clearance time
of 54 ms have been reported
2
. New analog and digital relays cover
an increasingly broader spectrum
3
. Evaluation of the utility test
practice has indicated that the steady state tests are not sufficient,
if the full behaviour of a relay design is to be evaluated
4
. This
demands the performance of high speed protection to be
evaluated and judged under condition close to those encountered
in real applications
5
.
The acceptance of new relays and the study of new principle
require a tool, which can accurately generate transient current and
voltage over a large bandwidth. Some studies also have indicated
that a detail relay performance evaluation require test signals
which closely correspond to the actual fault signals
6, 7
.
A number of different test equipment capable of generating fault
transients were designed and developed in the past. These design
include analog physical model of power system, hybrid electronic
design and digital simulators
1, 8, 9
. Those simulators can be used
for dynamic testing of relays. But their cost restricts wide use in
utility environment. Moreover, there are tests which cannot be
done manually due to the fact that manual control of injection
amplifier is too slow and dynamic fault conditions cannot be
simulated with these devices.
Some authors have described computerised testing as an aid to
the development of new design of protective relays
10
. Need spe-
cific computer aided relay testing can effectively be used to assists
in reaching the outlined aims for relay maintenance in fu-
ture
11, 12
.
This paper describes the implementation detail of a comput-
erised dynamic testing of protective relaying scheme. Design
of a digital simulator with various test configurations is described
in this section. Use of the simulator for testing of a relay is also
outlined.
DESIGN OF A COMPUTERISED DYNAMIC
TEST SET
The details of the functional block diagram is shown in
Figure 1.
In this scheme transient fault signals to be used for testing the
desired relay may be generated by three methods:
(a) by using alternative transient program (ATP),
(b) by using synthetic waveforms generated by Fourier series,
(c) by decoding digital fault recorder (DFR) signals.
The signals obtained by any one of the above methods is being
fed to an output interface by means control program. The output
interface consists of a 3-phase DA converter (DAC) and a 3-phase
current amplifier. The output signals from the current amplifier
are then used to test the 3-phase over current relays.
A K Maitra is with the Department of Electrical Engineering, B E
College (DU), Howrah 711 103 and A Rakshit and S K Basu are with
the Department of Electrical Engineering, Jadavpur University, Kolkata 700
032.
This paper (redrafted) was received on December 1, 2002. Written discussion on
this paper will be received until November 30, 2003.
86
IE(I) Journal-EL FUNCTIONS OF THE CONTROL PROGRAM
The control program has the following functions
(i)
The control program can accept three single column data
file of current waveforms for three individual currents,
either obtained by ATP simulation or by decoding DFR
signals, or signals received by utilising Fourier series
techniques.
(ii) An interrupt driven program is included in the control
program to drive the 3-phase DAC interface through
parallel port according to the sampling frequency
f
s

= 1

T, where T is the time step used in ATP
simulation. The mode of operation may be single, multiple
or continuous.
(iii) A 3-channel digital interface is being provided to sense the
trip condition of the relay contact and to compute the
operating time of the relay.
(iv) After the tripping, the current excitation to the relay under
test is automatically stopped.
DESIGN OF THE OUTPUT INTERFACE
DA Converter
A 3-phase 12 bit DA converter converts the 3-phase digital
current waveform data to analog form before they are being used
as an input to the three current amplifiers. The block diagram of
the DA converter is shown in Figure 2.
A PC usually does not have the built-in facility to provide all these
3
×12 = 36 bit (digital lines) needed to the drive 3-phase DAC
interface. Parallel to serial and serial to parallel conversion are
adopted with limited number of output lines available from the
PC parallel port. This interface provide excitation to three current
amplifiers which inturn feed test signals to relay under test.
Inside the PC data is multiplexed (at parallel port) through soft-
ware and demultiplexed inside the DAC interface unit through
proper hardware. The digital signals from control program are
converted into analog signals by a 3-phase DAC interface. A
separate 3-phase DAC interface is designed for conversion of
digital current signals into corresponding analog voltage signals
to drive the 3-phase current amplifier. Data transfer takes place
in byte-serial bit-parallel fashion. A part of the parallel port has
been utilised for transmission of software multiplexed data seri-
ally to the DAC interface. Serial to parallel conversion is done by
five 8-bit serial to parallel shift registers. Inter phase relation or
delay remains same before and after transmission. A part of the
status port is utilised to sense the relay trip condition.
The DAC interfaces are so designed that no remarkable time delay
occurs between the digital input voltage wave forms data and of
analog output voltage wave forms.
Design of Current Amplifier
The basic circuit of the current amplifier is shown in Figure 3. It
uses complementary pair of MOSFET devices M
1
, M
2
as the
output stages. Split power supply rails
(±
V
D
) are used for giving
improved rejection of power supply ripples and allowing the load
to be directly coupled. The output devices M
1
and M
2
operate in
source follower configuration. This offers two fold advantages,
(i) the possibility of oscillation in the power output stage is
reduced as the voltage gain is nearly unity and (ii) the signal
feedback through the heat sink is eliminated as the drain terminal
is electrically connected to the dc voltage.
Figure 1 Functional block diagram of the test set
Figure 2(b) Detail block diagram of DA converter
Figure 2(a) Functional block diagram
Vol 84, September 2003
87 Symmetrical output is achieved by providing proper drive to the
gate circuit of the MOSFETS. Negative feedback from the output
of the amplifier is fed to the inverting input of the operation
amplifier.
Since higher rating P-channel MOSFETS are not readily available
so N-channel MOSFETS in both halves are used in the modified
circuit. P-channel MOSFETS in lower half of the circuit is re-
placed by its equivalent N-channel MOSFET along with gate
drive circuit.
Six N-channel MOSFETS (IRF640) are paralleled in each
half to increase the current rating of the amplifier. Paralleling of
MOSFETS is a much easier task than using bipolar transis-
tors
13
. It has been found that the amplifier is susceptible to
oscillation due to the presence of stray capacitances and induc-
tances. To prevent oscillation due to stray cap