nt day size of 0.1
µ
m.
To enable transistor scaling into the 21
st
century, new
solutions such as high dielectric constant materials for
gate insulation and shallow, ultra low resistivity
junctions need to be developed. In this paper, for the
first time, key scaling limits are quantified for MOS
transistors (see Table 1). We show that traditional SiO
2
gate dielectrics will reach fundamental leakage limits,
due to tunneling, for an effective Transistor-Challenges-for-the-21st-Century/' >electrical thickness
below 2.3 nm. Experimental data and simulations are
used to show that although conventional scaling of
junction depths is still possible, increased resistance for
junction depths below 30 nm results in performance
degradation. Because of these limits, it will not be
possible to further improve short channel effects. This
will result in either unacceptable off-state leakage
currents or strongly degraded device performance for
gate lengths below 0.10
µ
m. MOS transistor limits will
be reached for 0.13
µ
m process technologies in
production during 2002. Because of these problems, new
solutions will need to be developed for continued
transistor scaling. We discuss some of the proposed
solutions including high dielectric constant gate
materials and alternate device architectures.
FEATURE
LIMIT
REASON
Oxide Thickness
2.3 nm
Leakage (I
GATE
)
Junction Depth
30 nm
Resistance (R
SDE
)
Channel Doping
V
T
=0.25 V Leakage (I
OFF
)
SDE Under Diffusion 15 nm
Resistance (R
INV
)
Channel Length
0.06
µ
m
Leakage (I
OFF
)
Gate Length
0.10
µ
m
Leakage (I
OFF
)
Table 1: Fundamental scaling limits for conventional
MOS devices
Introduction
For more than 30 years, MOS device technologies have
been improving at a dramatic rate [1,2]. A large part of
the success of the MOS transistor is due to the fact that it
can be scaled to increasingly smaller dimensions, which
results in higher performance. The ability to improve
performance consistently while decreasing power
consumption has made CMOS architecture the dominant
technology for integrated circuits. The scaling of the
CMOS transistor has been the primary factor driving
improvements in microprocessor performance.
Transistor delay times have decreased by more than 30%
per technology generation resulting in a doubling of
microprocessor performance every two years. In order to
maintain this rapid rate of improvement, aggressive
engineering of the source/drain and well regions is
required. In this paper, key methods for improving device
performance are discussed. Creating shallow source/drain
extension (SDE) profiles for improved short channel
effects, the use of retrograde and halo well profiles to
improve leakage characteristics, and the effect of scaling
the gate oxide thickness are discussed in detail.
Fundamental tradeoffs and scaling trends in engineering
these effects are analyzed through experimental data and
computer simulations. The impact of these trends
associated with circuit requirements including power
supply, threshold voltage, and off-state leakage on
transistor design is also explored. We show that the
scaling trends of the last ten years will be extremely
difficult if not impossible to maintain unless new
methods for device improvement are found. In addition
to the conventional MOS transistor, several alternate
device architectures are analyzed to understand the
potential gains and tradeoffs associated with each device.
The ability to overcome current physical technology
limits such as gate oxide thickness and shallow junction
formation as well as tradeoffs in circuit design will Intel Technology Journal Q398
MOS Scaling: Transistor Challenges for the 21st Century
2
determine if MOS transistors can be scaled into the next
century.
Oxide Scaling
Gate oxide thickness scaling has been instrumental in
controlling short channel effects as MOS gate
dimensions have been reduced from 10
µ
m to 0.1
µ
m.
Gate oxide thickness must be approximately linearly
scaled with channel length to maintain the same amount
of gate control over the channel to ensure good short
channel behavior. Figure 1 plots the Transistor-Challenges-for-the-21st-Century/' >electrical channel
length divided by gate oxide thickness for Intels process
technologies over the past 20 years. Each data point
represents a process technology, developed approximately
every three years, which was used to fabricate Intels
leading-edge microprocessors.
0
10
20
30
40
50
60
0.01
0.1
1
10
NMOS L
E
L
E
/ T
OX
0.01 0.1 1 10
NMOS L
E
(
µ
m)
L
E
/ T
OX
1
60
50
40
30
20
10
0
L
E
= 45 * T
OX
Source: Intel Process
technology over 25 years
Figure 1: Channel length divided by gate oxide
thickness versus channel length
From Figure 1, a simple relationship between oxide
thickness and the minimum channel length set by short
channel effects is observed:
L
E
= 45 * T
OX
(Eq. 1)
This relationship exists because the channel depletion
layer is engineered to become smaller as the gate oxide
thickness is decreased. In addition, short channel
behavior is governed by the ratio of channel depletion
layer thickness to channel length. The channel depletion
layer is inversely proportional to the square root of the
channel doping concentration. During device
optimization, channel doping is increased as the oxide is
scaled to maintain approximately the same device
threshold voltage. Figure 2 illustrates this point. In
Figure 2, the thickness of the channel depletion layer for
two devices with different oxide thicknesses is shown.
Figure 2a shows the depletion layer for a device with an
oxide thickness of 4.5 nm while Figure 2b shows a device
with an oxide thickness of 3.2 nm.
(b)
Source
Drain
Si - Gate
Source
Drain
Si - Gate
0.3 0.4 0.5 0.6 0.7
(a)

µ
m
0.3 0.4 0.5 0.6 0.7
0.1
0.0
0.1
0.2
0.1
0.0
0.1
0.2
-
-
Figure 2a and 2b: Device simulations showing channel
depletion layer thickness for devices with two oxide
thicknesses: (a) 4.5 nm, (b) 3.2 nm
Both devices have the same off-state leakage. The device
with the thinner oxide has a smaller channel depletion
layer and hence improved short channel characteristics.
The improved short channel effects can be taken
advantage of by targeting a smaller channel length.
Thus, for continued MOS channel length scaling, the
gate dielectric thickness must continue to be scaled.
Figure 3 shows the Semiconductor Industry Associations
(SIA) road map for gate dielectric thickness. This
roadmap predicts that continued gate dielectric scaling
will be required with a new gate dielectric material
needed for the 2002-2005 time frame.
0
1
2
3
4
5
6
250
180
150
130
100
70
50
Technology Dimension (nm)
Electrical T
OX
(nm)
1997 1999 01 03 06 09 2012
SiO
2
Advanced Gate
Dielectric Required
.25 .18 .15 .13 .10 .07 .05
Technology Dimension (
µ
m)
6
5
4
3
2
1
0
T
OX

EFF
(nm)
Figure 3: SIA road map for junction depth Intel Technology Journal Q398
MOS Scaling: Transistor Challenges for the 21st Century
3
Scaling Limit for SiO
2
SiO
2
or nitrided SiO
2
has been the gate dielectric used by
the semiconductor industry for over 30 years. The
thickness limit is the same for both materials and is not
limited by manufacturing control. Today, it is
technically feasible to manufacture 1.5 nm and thinner
oxides on 200 mm wafers [3]. The thickness limit for
SiO
2
is set instead by gate-to-channel tunneling leakage.
Figure 4 schematically shows the tunneling leakage
process for an NMOS device biased in inversion.
N
+
Gate
e
-
P
-
Substrate
Figure 4: Direct tunneling leakage mechanism for thin
SiO
2
As the thickness of the dielectric material decreases,
direct tunneling of carriers through the potential barrier
can occur. Because of the differences in height of barriers
for electrons and holes, and because holes have a much
lower tunneling probability in oxide than electrons, the
tunneling leakage limit will be reached earlier for NMOS
than PMOS devices. The SiO
2
thickness limit will be
reached approximately when the gate to channel
tunneling current becomes equal to the off-state source to
drain sub-threshold leakage (currently ~1nA/
µ
m).
Figure 5 shows the area component of gate leakage
current in A/cm
2
versus gate voltage. If we assume the
gate leakage limit occurs for devices with 0.1
µ
m gate
length designed for 1.0V operation, the SiO
2
thickness
limit occurs at ~1.6 nm.
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
0
1
2
3
Gate Voltage (V)
Gate Current (A/cm
2
)
15 A
20 A
25 A
29 A
32 A
36 A
nMOSFET
Simulation
0 1 2 3
Gate Voltage (V)
I
GATE
(A/cm
2
)
10
-8
10
4
10
0
Figure 5: Gate leakage versus gate voltage for various
oxide thicknesses [5]
We now have established that the thickness limit for SiO
2
is ~1.6 nm. However, due to quantum mechanical and
poly-Si gate depletion effects, both the gate charge and
inversion layer charge will be located at a finite distance
from the SiO
2
/Si interfaces with the charge location
being a strong function of the bias applied to the gate.
Figure 6 shows the location of the inversion layer charge
in the silicon substrate for a transistor with a typical bias
when quantum mechanical effects are taken into account
[4]. The centroid for the inversion charge is ~1.0 nm
from the SiO
2
/Si interface. This increases the effective
SiO
2
thickness (T
OXEFF
) by ~0.3 nm. By taking into
account the c