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Semiconductor IC Test and Design-for-Test Fundamentals
Semiconductor IC Test and Design-for-Test Fundamentals
By Al Crouch, Chief Scientist, Inovys Corporation


The Semiconductor Industry seeks to reduce the cost of manufacturing its product by
continuously reducing the per-part recurring costs in the following manner:

- Reduction of silicon cost by increasing volume and yield, and by die size reduction
(process shrinks or more efficient layout)

- Reduction of packaging cost by increasing volume, shifting to lower cost packages if
possible (e.g., from ceramic to plastic), or reduction in package pin count

- Reduction in cost of test by:
- reducing the vector data size
- reducing the tester sequencing complexity
- reducing the cost of the tester
- reducing test time
- simplifying the test program

Design for test contributes to all three fundamental strategies.
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Introduction
Currently, the semiconductor industry is changing on many fronts:

smaller geometric features on silicon;

the reduction of internal voltage levels;

the use of new physical processing techniques such as copper interconnect,
low-K dielectrics, and silicon-on-insulator,

the use of complex megacells and macrocells known as cores;

the use, and reuse, of existing simple and complex "hard" macrocells;

the integration of huge amounts of memory; and the integration of large

amounts of logic on system-on-a-chip devices.
These industry changes make quality and reliability requirements more important than
ever, but at the same time are creating aggressive challenges in the ability to measure the quality
level, or to measure the quality level economically. For example:
The smaller features, lower operating voltages, and new processing
techniques are expected to create new classes of defects and
failure effects, such that existing defect, fault, and failure models
may be inadequate for detection and characterization.
The ability to place large volumes of logic and memory on a
single die in a short period of time is expected to increase the
cost-of-test due to longer test times and larger amounts of test
vector data, and is also expected to compress the design cycle time
involved with the DFT portion of the chip.
The ability to use complex cores and reuse macrocells is expected
to create access and vector delivery problems with design
elements that may be quite testable as stand-alone devices, but are
to be embedded or doubly embedded within the overall chip
architecture (macrocells or memory arrays are included with other
macrocells that will be embedded).
In the past, the test process has been characterized as an "over-the-wall" event that
occurred when the design team completed the design and threw it to a dedicated team of test
and/or verification professionals. This test process was largely the translation and reuse of the
functional simulation verification vectors to the target tester platform. and the manual creation of
new verification vectors to get more coverage. The vectors were laboriously "graded" for fault
coverage by conducting fault simulation. The "post design" time to provide a set of vectors to
meet high quality expectations was measured in months and even years. The new test issues
have now required that test structures be designed into the device to assist with the test process,
quality measurement, and the vector generation. These changes are being driven by market
pressures to: 1) provide high-quality parts (Quality/Reliability); 2) meet time-to-market or time-
to-volume manufacturing windows (TTM/TTV); and 3) meet product cost goals by meeting
cost-of-test goals (COT). Figure 1-1 illustrates this trend.
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Concurrent Test Engineering
The rapid pace of process geometry reduction in recent times has led to a strange cost/
pricing effect. Whereas in the past, the overall cost of the semiconductor product has been able to
be cost managed to a lower level over time, lags in supporting technology have finally led to
"smaller is more expensive." There is currently a reasonable die size limit to the ability to con-
nect bonding wires from the package to the silicon. This has led to a somewhat "limited" die size
for certain pin count packages. If a process geometry shrink is applied to an existing device, then
the logic may not fill up the space within the pad ring. To eliminate this "white space; the chip
design organizations are adding more functionality or memory arrays. These significantly
increase test time and test vector data. If the memory supported on the chip, or the additional
memory added, is a non-volatile memory (Flash, EEPROM), then test time is also significantly
increased, since these types of memories require long test times naturally.
Another test cost impact has been the adoption of the "reuse" hard core macrocell (for
example, an entire microprocessor as a megacell). For intellectual property (IP) security reasons,
hard core macrocells from core providers are delivered complete with existing test vectors (hav-
ing the ability to generate vectors against a structural description of a provider's core may give
away all the proprietary internal features for the core). Semiconductor devices made with many
hard cores require building test programs out of many vector sets delivered by the core providers.
The vector sets may not be very efficient, or may not be able to be applied simultaneously to
other vector sets. This fact leads to a high cost-of-test in having a complicated "patchwork" test
program.
The only way to manage the ever-increasing cost-of-test problem is to apply design-for--
test techniques to the device during the design phase-this concept has been called concurrent
engineering in the past. In reality, the test needs of modern state-of-the-art devices will require
that test considerations become an inseparable part of the design process, and the cost-of-test
problem can be treated just like any other engineering budget (area. power, frequency, noise
immunity, electrostatic discharge immunity, etc.) and techniques can be applied to manage it as
part of the overall design (see Figure 1-2). The key optimization factors are the amount of vector
data, the complexity of the tester operation and pin timing management, the expense impact of
the target tester, the total "in-socket" test time, and the average quality level measurement per
vector or per second (the vector efficiency).
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Figure 1-2 Design process
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Figure 1-3 Why Test?
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The Reasons for Testing
Why Test? Why Add Test Logic?
Basically, there are two real reasons to conduct testing. As shown in Figure 1-3, it is con-
tractually required by a specific customer (or by generic customers by way of an implied or
actual warranty); or it is required by a competitive environment where the quality level and
device reliability are among the items voted on by customer dollars.
Test logic may be added for several reasons. Some key reasons cited quite often are
"to increase the test coverage" and "to reduce the time it takes to qualify the part" (deliver
vectors that meet a certain test coverage). Many organizations are now beginning to understand
that "reducing the cost-of-test" by supporting test features during the design phase is
manageable, achievable, and can be treated as an engineering problem with a set of targetable
goals. The act of adding logic or features to enhance the testability of a design is generally
referred to as Design-for-Test (DFT). More specifically, DFT can be defined as adding logic or
features to enhance the ability to achieve a high quality metric, to ease the ability to generate
vectors, to reduce the time involved with vector generation, or to reduce the cost involved with
the application of vectors.
Pro and Con Perceptions of DFT
Whenever testing and design-for-test is brought up as a subject, people and organizations
have differing opinions and perceptions. For design engineering organizations and individuals,
the perception of DFT is generally negative:

it adds work and complication to the design methodology flow

it negatively impacts chip design budgets such as
o power area timing
o package pin requirements

it adds tasks and risk to the design schedule

However, for test professionals, the perceptions of DFT are usually positive and include
such items as:

having the ability to measure the quality level deterministically

making it easier to generate the necessary vectors;
making i