UNIVERSITY OF CALIFORNIA Santa Barbara 1.0 - 2.0 GHz Wideband PLL CMOS Frequency Synthesizer A thesis submitted in partial satisfaction of the requirements for the degree of Master of Science in Electrical and Computer Engineering by Chao W. Huang Committee in charge: Professor Forrest D. Brewer, Chair Professor Steve E. Butner Professor P. Michael Melliar-Smith June 2004 The dissertation of Chao W. Huang is approved. Steve E. Butner P. Michael Melliar-Smith Forrest Brewer, Committee Chair June 2004 1.0 - 2.0 GHz Wideband PLL CMOS Frequency Synthesizer
Copyright © 2004 by Chao W. Huang All rights reserved iii Abstract 1.0 - 2.0 GHz Wideband PLL CMOS Frequency Synthesizer by Chao W. Huang CMOS mixed-signal design has become very popular in today's semiconductor industry. This paper is to demonstrate a CMOS frequency synthesizer design, whose primary purpose is to test the designer's high speed, mixed-signal CMOS circuit design skill. The design uses 0.25um deep sub-micron CMOS process technology. Thus issues such as noise rejection, high frequency parasitic effects, leakage current, power dissipation, etc. can be exposed and the designer's problem solving skills can be exercised. A new counter design, the "modified Möbius counter" is also presented in this design. Furthermore, this design is used to verify the usability of the previously set up custom design flow and standard cell design flow, which may be used for future academic teaching purpose. iv Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 INTRODUCTION TO THE FREQUENCY SYNTHESIZER . 4
2.1 2.2 2.3 2.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Frequency Synthesizer Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Phase Noise and Timing Jitter Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 PHASE-LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Voltage-Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Design of VCO Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.1 3.2.1.1 3.2.2 3.3 Design of VCO Switching Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Design Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.1 3.3.2 3.4 3.5 3.6 3.7 Phase-Frequency Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PLL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Physical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 v 4 COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Design and Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Modified Möbius Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.2.1 4.2.2 4.2.3 4.3 4.4 4.5 Simulation and Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Physical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5 PADS AND PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.1 5.2 5.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 High Speed Differential Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 General Purpose Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ESD Protection Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Power Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Analog Power Pads and Reference Pad . . . . . . . . . . . . . . . . . . . . . . . . 62 Digital I/O Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.1 5.3.2 5.3.3 5.3.4 5.4 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6 OTHER DESIGN ISSUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.1 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 vi 6.3 6.4 6.5 Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Design for Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Dummy Metal/Pad Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7 WHOLE CHIP SIMULATION AND TEST PLAN . . . . . . . . . 73
7.1 7.2 7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Whole Chip Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Test and Measurement Plan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8 CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 vii List of Figures
2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 Simplified block diagram and waveforms for a frequency synthesizer. .........5 PFD phase error vs. Vout plot..........................................................................6 State diagram and schematic of PFD..............................................................7 Sample waveforms for PFD/CP/LPF combination.........................................7 Schematic of a charge pump...........................................................................8 Linear model of the frequency synthesizer...................................................10 Schematic of modified loop filter..................................................................10 VCO block diagram......................................................................................15 n-stage inverter oscillator VCO () ................................................................17 Schematic of ring oscillator delay stage. ......................................................17 Step response when Vi+: 0->1 ......................................................................19 RC model of a 2-stage ring oscillator...........................................................20 Example of the 2-stage VCO output as a function of Vctrl..........................22 Schematic of VCOs switch unit S1 (single-ended version). ........................23 Schematic of VCOs switch unit S2 (single-ended version). ........................24 MATLAB Simulink PLL model. ..................................................................27 Simulink simulation output for N=1000.....................................................27 MOS capacitor structure and its characteristic plot....................................29 Differential CP/LPF unit. ...........................................................................30 Current source for CP/LPF unit..................................................................31 viii 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 Common-mode feedback amplifier. ...........................................................32 Schematic for phase-frequency detector unit. ............................................33 Schematic of single-ended-to-differential signal converter. .......................34 Simulated differential VCO control voltage...............................................35 Simulated reference and feedback signals..................................................35 Simulated control voltage after the PLL is locked. ....................................35 Full-custom design flow..............................................................................36 Layout plot of PLL block. ..........................................................................37 Pulse swallow frequency divider. .................................................................40 Block diagram of counter unit. .....................................................................41 4-bit Möbius counter counting pattern. ........................................................43 schematic of a 4-bit Möbius counter.............................................................43 Pattern edge detection circuit. ......................................................................45 64-count 2 stages Möbius counter. ...............................................................46 Schematic of 256-state programmable counter. ...........................................47 (249/372)-state fixed counter. .......................................................................48 3/2 prescaler..................................................................................................49 Sample waveforms from 1-256 programmable counter. ............................51 Typical Standard Cell Design Flow. ...........................................................53 Layout plot of programmable counter design.............................................54 Layout plot of 8-bit shift register................................................................54 Layout plot of 4-16 decoder design............................................................55 ix 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 6-1 7-1 Schematic of high speed differential pad drivers..........................................59 Layout plot of differential pads. ...................................................................60 ggMOS ESD protection scheme...................................................................61 A pad structure with ggMOS ESD protection. .............................................62 Schematic of power pads. .............................................................................62 Schematics for analog power pads and reference pad. .................................63 Schematic of the bi-directional digital pad...................................................64 Layout plot of the bi-directional pad. ...........................................................64 Pin model of CLCC-44 package...................................................................65 Layout plot of frequency synthesizer design (including pads)...................66 Metal and assembly stress relief fill. ............................................................72 Setup of top-level simulation........................................................................74 x List of Tables
3-1 3-2 The frequency synthesizer's design specification.........................................14 Parameters for manual model of generic 0.25CMOS process (minimum length device)......................................................................................16 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 4-1 5-1 5-2 7-1 Device sizes for the VCO delay cells. ..........................................................21 Corner case Kvco values. .............................................................................22 Device sizes for the switch unit S1...............................................................23 Device sizes of VCOs switch unit S2. ..........................................................24 CP/LPF design values...................................................................................26 Device sizes of CP/LPF unit.........................................................................30 Device sizes of current source. .....................................................................31 Device sizes for common-mode feedback amplifier...................................32 Counting values for the pulse swallow frequency divider. ...........................40 Device sizes of high speed differential pad drivers. .....................................60 Device sizes for the bi-direction pad. ...........................................................64 Test result of whole chip simulations. ..........................................................75 xi 1 INTRODUCTION PLL-based frequency synthesizers are used in many electronic applications. In the past, frequency synthesizers were mainly implemented by using discrete components. However, due to the package electrical characteristics, building a frequency synthesizer with discrete components to meet the advancing design speed constraint becomes more and more difficult. This is more obvious in the growing wireless communications market. In a wireless communication system, to achieve higher speed, lower cost, smaller form factor, and lower power dissipation, the frequency synthesizer is usually integrated together with other circuits in low-cost CMOS technology. This in turn requires enough supply-noise isolation for the synthesizer to provide low phase-noise output. Because of its good supply noise and common-mode noise rejection properties, the differential structure is commonly used in on-chip frequency synthesizer design. Another issue of on-chip synthesizer design is the difficulty of generating output with wide frequency tuning range. This is because to have wider output frequency tuning range, larger capacitance is required. Since current CMOS technologies do not provide good capacitance/area ratio, it is expensive to build a large capacitor and therefore, limits the synthesizer's output tuning range. In order to increase the tuning range without increase the chip area usage, multi-VCO unit can be used. The idea is to partition 1 output frequency range into sections, one VCO is responding to one section. A multiplexer unit is used to direct the valid VCO output to the synthesizer output. Therefore, with multi-VCO structure, wider tuning range can be achieved with limited capacitance area usage. One of the core components in the frequency synthesizer is the programmable counter. Traditional counter designs are normally based on either binary or one-hot design structure. Binary counter structure is chip-area efficient but gives slow performance. On the other hand, one-hot design provides good speed performance, but is chip-area expensive. Due to these limitations, in a high-speed and wide-tuning-range synthesizer, neither binary nor one-hot design structure may be usable for programmable counter design. Therefore, a new counter design structure is necessary. In the following chapters, we will demonstrate the design and implementation of a frequency synthesizer by using the concepts described about. Also, we will present a new counter design, the so-called modified Mobius counter. This counter structure can provide speed performance comparable to one-hot design while using limit amount of chip area. It also gives the benefits of lower power consumption and glitch-free output. We will also briefly discuss the custom design flow and standard design flow that are used in this design. To complete the demonstration, we will also cover the design and construction of high-speed differential pad and generic pads circuits. Lastly, we will discuss the IC test and measurement plan for the design. The complete synthesizer 2 design implementation complies with TSMC 0.25 µm CMOS technology and the prototype is sent out on May 17th, 2004 for fabrication. 3 2 INTRODUCTION TO THE FREQUENCY SYNTHESIZER 2.1 Introduction
The frequency synthesizer's simplified block diagram is shown in Figure 2-1. In the frequency synthesizer, the PLL block is responsible for generating an output signal whose frequency is dependent on the phase relationship between two input signals. The phases of a reference signal, fref, and a feedback signal, ffb, are compared in a phasefrequency-detector (PFD), and the phase difference is then converted by a charge pump and low pass filter (CP/LPF) circuit into a control voltage. This voltage controls the VCO to generate a signal with the desired frequency. A divider is inserted on the feedback path, giving
f fb = f out ÷ M . Since in the locked condition, fref and ffb must be equal, fout is simply equal to the product of fref by M. Shown in Figure 2-1(b) are the simple waveforms with M=4. By changing the multiplication factor, M, signals with desired frequency can be generated. In order to understand and analyze the functional behavior of the frequency synthesizer, it is necessary to construct a linear model for the system. As we will see, the frequency synthesizer is a non-linear device but it can be modelled as a linear device since under 4 Figure 2-1. Simplified block diagram and waveforms for a frequency (a) Block diagram (b) Typical waveforms with M=4 normal operation, the system behaves fairly linearly. In this chapter, we will start by briefly discussing each building block and its linear model. We will then combine the models and analyze the synthesizer system as a whole. Since we intend to concentrate on circuit design here, an in-depth discussion of each building block and its model is beyond the scope of this thesis. More information can be acquired from [Dai03] and [Rabaey02]. 2.2 Frequency Synthesizer Basics
As seen in Figure 2-1(a), the frequency synthesizer has four sub blocks: PFD, CP/LPF, VCO, and feedback divider blocks. The PFD block is used to determine the phase difference between the reference and feedback signals. Depending on the input signals' phase relationship, i.e. one leads or lags the other, the PFD produces an appropriate output signal. This is best described with the PFD phase characteristics plot shown in 5 Figure 2-2, in which, = phase ref ­ phase feedback . The plot shows that the PFD is a nonlin- ear device and it has a linear phase range within 360 degrees. When the synthesizer is in locked state, the phase error between feedback and reference signals are normally small, which is well within the PFD's linear operating region. Therefore, in locked mode, we can consider the PFD block a linear device. Figure 2-2. PFD phase error vs. Vout plot. The phase frequency detector described above can be implemented by a digital state machine, whose state diagram and schematic are shown in Figure 2-3. The PFD design produces non-complementary outputs UP and DN. The UP signal is used for increasing the value of control voltage and therefore, increasing the output frequency of the VCO. A DN signal does the exactly opposite job, and is used for lowering the output frequency. The duty cycle of each signal is dependent on the phase relationship between the two input signals and their phase difference. Assuming fref is leading, the DN signal 6 remains inactive while the UP signal become active with a duty cycle of ------ , 2 as shown in Figure 2-4. When ffb leads, the UP and DN signals behave exactly the opposite.
Figure 2-3. State diagram and schematic of PFD (a) State diagram (b) Schematic Figure 2-4. Sample waveforms for PFD/CP/LPF combination. Since the UP and DN signals are digital signals, they must be converted into an analog voltage to control the VCO. A charge pump and a low-pass filter unit serves the purpose. Shown in Figure 2-5 is one possible implementation of a CP/LPF unit. It consists of two switched current sources that pump charges into or out of the low-pass filter 7 according to the PFD outputs. VCO control voltage, Vout, rises when UP is active and the amount of voltage change is dependent on the duty cycle of the UP signal, which can be seen in Figure 2-4. Similarly, Vout decreases when DN is active.
Figure 2-5. Schematic of a charge pump
Vdd Icp UP Vout DN CP Icp Gnd Gnd Let us consider the case when the reference clock is leading the feedback clock. The average output current from the charge pump is then given by
t UP ­ active I out = I cp ------------------------- . T ( 2-1)
t UP ­ active ------------------------T In which, T is the period of the reference frequency. Therefore, duty cycle of UP signal. Thus, we have
I out = I cp ------ . 2 is simply the ( 2-2) Equation 2-2 can be applied to the cases when the feedback signal is leading the reference clock as well, with both phase error and output current negative. Hence, the transfer function of the PFD and charge pump can be expressed as 8 I out I cp -------- ( s ) = ------ . 2 ( 2-3) In simplest case, a low-pass filter can be made as one capacitor connected from limitedimpedance signal line to ground, as shown in Figure 2-5. Its transfer function is then given by
V out 1 ---------- ( s ) = ------------ . I out s Cp ( 2-4) The output voltage from the low-pass filter is fed into the voltage-controlled oscillator unit. There are two types of VCO designs that are widely used in the industry, ring oscillator VCO and LC VCO. An LC VCO offers good phase noise performance. However, its requiring special fabrication process, occupies much bigger area, and narrow tuning range properties make it unsuitable to be used in our design. Therefore, we choose to use a ring oscillator for the VCO. The transfer characteristic of a VCO unit can be described as
f vco ( t ) = K vco × V out ( t ) . ( 2-5) Integrating on both sides, we have
vco ( t ) = K vco V out ( t ) dt ,
0 t ( 2-6) yielding the transfer function
out K vco ---------- ( s ) = ----------- . V out s ( 2-7) The output signal generated by the VCO unit is then fed back to the PFD via a divider unit. The feedback divider carries the function
f in = M f out , which is in our case, 1 f fb = ---- f vco . M 9 With each sub system's linear model defined, we can now construct a linear model for the frequency synthesizer system. The combined synthesizer's linear model is shown in Figure 2-6. The model gives a closed-loop transfer function
K vco I cp 1 ------ ------------ ----------s 2 s C p out ( s ) H ( s ) = ------------------ = ------------------------------------------------------------ . K vco in ( s ) 1 1 I cp ---- ------ ------------ ----------1+ s M 2 s C p ( 2-8) Figure 2-6. Linear model of the frequency synthesizer. Figure 2-7. Schematic of modified loop filter. Icp R C2 Cp Vout With C2 1
Vdd M3 current path 1 M5 M7 Vi- '1' Vo- '0' Vo+ Vi+ M2 M4 M6 current path 2 Gnd At t=0, both M2 and M7 are on, and creating the two current paths shown in the figure. Since M3 and M6 are still on, the output states remain unchanged until when Vo+ = VTN or Vo- = Vdd + VTP. At that moment, either M4 or M5 turns on. Due to the positive feedback formed by the latch pairs, both outputs switch states rapidly. Now, let us define this is the threshold point of the delay stage, in which, Vi+ = Vth and Vi- = Vdd - Vth. At threshold point, M2 and M7 are in saturation and M3 and M6 are in linear mode. On "current path 1", we have
W M3 k n W M2 V TP 2 I d = ------ ----------- ( V th ­ V TN ) = k p ----------- ( V TN ­ V dd ­ V TP )V TP ­ --------- . L M3 2 L M2 2
2 (3-1) Solving for Vth, we get
W M3 L M2 V TP = V TN + 2 ----------- ----------- ( V TN ­ V dd ­ V TP )V TP ­ --------- . L M3 W M2 2
2 V th (3-2) When each NMOS and PMOS pair have equal strength, Equation 3-1 and Equation 32 also apply to "current path 2". Notice that when the size of the latches and all the gate lengths stay constant, Vth is just a function of the inverters' effective width. 19 Now, let us study the relationship between the threshold voltage and oscillator output frequency by using the 2-stage oscillator as an example. The basic RC model and example waveforms are shown in Figure 3-5. Rd is the equivalent drive resistor and Cg is the equivalent input capacitor of a delay stage. In order for the system to oscillate, VTPB must cross over the delay cell threshold voltage Vth at
T t = -4 after VTPB starts rising, so that it can trigger the next stage. Therefore, we have the following equation:
Figure 3-5. RC model of a 2-stage ring oscillator
Vdd V (t) Gnd TPA TPA TPB TPC Vdd - V V TPB (t) th Rd Rd Cg Cg V th t=0 Gnd delay cell Gnd delay cell Vdd V (t) Gnd t=T/2 t=T TPC (a) RC model (b) Waveforms at nodes TPA and TPB ­ -----------------­ ------------------ V dd T 4RdCg 4RdCg V th = V TPB -- = V dd 1 ­ e . + -------------------------- e T 4 ----------------- 2RdCg 1+e T T (3-3) Solving for T, we get
V dd + ( 3V dd ­ 2V th ) ( 2V th ­ V dd ) T = 4RdCg ln --------------------------------------------------------------------------------------- . 2 ( V dd ­ V th ) (3-4) According to [Dai03], the circuit noise can be viewed as equivalent to a variation in the
dT threshold voltage, Vth. Thus, to minimize noise, we want ----------- to be as small as possible. dV
th Solving Vth from Equation 3-4, we get
V th 0.8V dd = 2.0V . (3-5) 20 Combining it with Equation 3-2, we have
W M3 L M2 ----------- ----------- 2.1 . L M3 W M2 (3-6) For a 3-stage oscillator, results can be obtained using similar analysis. Optimal Vth for a 3-stage oscillator is Vth=1.8V. Therefore,
W M3 L M2 ----------- ----------- 1.6 . L M3 W M2 (3-7) Equation 3-6 and Equation 3-7 only give the optimal size relationship between latch and inverter pair. We thus use them as a guideline and use HSpice to find the transistor sizes that give both similar oscillators gain and optimal noise performance. Table 3-3 lists the device sizes for the VCO cells we use in our design.
Table 3-3. Device sizes for the VCO delay cells. Cell Delay cell for 2 stage VCO Delay cell for 3 stage VCO Device(s) M W ( µm ) L ( µm ) M W ( µm ) L ( µm ) M1/M7 3 35 0.24 12 8.75 0.24 M2/M8 3 14 0.24 12 3.5 0.24 M3/M5 3 15 0.24 2 10 0.24 M4/M6 3 6 0.24 2 4 0.24 M9 2 52 0.24 2 17.5 0.24 M10 2 21.4 0.24 2 7 0.24 Figure 3-6 shows a sample HSpice plot of the 2-stage VCO output period vs. control voltage, confirming that
out ----------V ctrl is a monotonic function within -0.1V to 2.5V control volt- age range. Acquired corner case Kvco values from simulation are listed on Table 3-4. Notice the Kvco/M values of the two VCO types are very close to each other. This gives us the ability to one CP/LPF for both VCO blocks in our design. 21 Figure 3-6. Example of the 2-stage VCO output as a function of Vctrl.
0.7n Period (sec.) 0.6n 0.5n 0.4n 0 0.5 1.0 1.5 2.0 2.5 Vctrl (V) Table 3-4. Corner case Kvco values. Sampling frequency VCO type Kvco (MHz/V) M Kvco/M (MHz/V) 120 2000 0.06 2.0 GHz 1.49 GHz 1.49 GHz 1.0 GHz 2-stage VCO 540 1490 0.36 90 1490 0.06 3-stage VCO 440 1000 0.44 3.2.2 Design of VCO Switching Units As mentioned before, it requires two extra switching units, as shown in Figure 3-1, in order to use one CP/LPF unit for multiple VCOs. We will now analyze the design analysis for both units. For simplicity, we use single-ended version designs in the following analysis. Let us first look at the design for Switch S1, whose schematic is shown in Figure 3-7. In the design, M1, M2, M3, and M4 form a passing gate MUX structure. According to the select signal SEL, the input VCO control signal is routed to either the A or B output. In order to reduce cross-coupling noise generated by the unused VCO 22 unit, we want to shut it off completely. Therefore, transistors M5 and M6 are added to the design so that when the VCO is not chosen, its control voltages are set to reversed maximum and thus, shut off the VCO completely. Because S1 connects the LPF unit and the VCOs, its parasitic value is added to the LPF gain. Thus, it is extremely important to keep the channel resistance down in order not to alter the LPF gain. In the technology we are using, a minimum size, W/L=1, fully on NMOS has an equivalent resistance value of 13 k and 31 k respectively for PMOS. Using the minimum sizing transistors for S1 will definitely break the linear model we use.
Figure 3-7. Schematic of VCOs switch unit S1 (single-ended version). IN SEL/ M2 M1 M3 M4 SEL/ M5 SEL M6 OUT0 Gnd OUT1 Gnd Table 3-5. Device sizes for the switch unit S1. Devices M W ( µm ) L ( µm ) Req ( ) M1/M3 12 10 0.24 26 M2/M4 12 25 0.24 25 M5/M6 12 2 0.24 130 23 To lower the equivalent resistance, Req, we can simply increase the transistors' W/L ratio, since Req is inversely proportional to the W/L ratio. The target Req is chosen to be less than 30 Ohm, which is compareable to interconnect wire resistance. Increasing the device sizes also increase their paracitic capacitances. In out final design, the overall paracitic capacitance of Switch S1 is approximately 210fF, which can be neglected, since Cp in the LPF unit which is in the picofarad range and hence dominates. The final device sizes are shown in Table 3-5. Notice that the sizes of M5 and M6 are small. This is because they are not on the LPF path, and therefore, their sizes do not affect the LPF gain and can be kept minimum.
Figure 3-8. Schematic of VCOs switch unit S2 (single-ended version).
IN0 IN1
SEL SEL/ M1 M2 M3 M4 SEL/ OUT Table 3-6. Device sizes of VCOs switch unit S2. Devices M W ( µm ) L ( µm ) M1/M3 1 2 0.24 M2/M4 1 5 0.24 Switch unit S2 uses a pass gate structure similar to that of S1. Its schematic is shown in Figure 3-8. Since S2 is used for passing high speed signals, we need to keep its input parasitic capacitance as low as possible so as not to create extra loads on the VCOs, 24 changing their gains. Thus, small size devices are used in S2, whose sizes are listed in Table 3-6 Once we have constructed the VCO unit and acquired the Kvco values, we can move on to the charge pump and loop filter designs. 3.3 Charge Pump and Loop Filter
From Equations 2-9, 2-11, and 2-16 we can see that the charge pump current Icp is inversely proportional to R, while R itself is directly proportional to Cp and C2. Since, in the process technology we are using, capacitors are expensive devices to make, we want to avoid the use of very large capacitors. To reduce the sizes of Cp and C2 while keeping
lpf , z , and p unchanged, we can cut down the charge pump current and increase the R value. Since resistors use a decent amount of area as well, it is wise to choose the values that give optimal space usage. 3.3.1 Design Analysis Before carrying on with further calculations, we need to choose the appropriate loop bandwidth for the filter. A rule-of-thumb selection is to make the loop bandwidth 1/10 of the PFD update rate [Razavi02], which is equal to the input reference signal in our case. Therefore,
2f ref 5 rad lpf = -------------- = 2 ×10 ------------ . sec V 10 Thus, we have 1 5 rad z = -- ×10 ------------ , sec V 2 and 3- 5 rad p = 8 ×10 ------------ . The lock-in time for a PLL with a PFD is approximated by Equation sec V 25 8, in which feo is the initial frequency error, N is the feedback divider ratio, and K is the loop bandwidth [Wolaver91].
8f eo T P ---------- . 2 NK (3-8) In our case, the worst case frequency error is 1.0 GHz, and the divider ratio is 1000. Therefore, the lock-in time is approximately 800 µs , which meets our design requirement. With all the above data given, we now can calculate the values for the R and C components and for the charge pump currents. Since the maximum overshoot of the control voltage occurs when the loop gain is minimum, we use the minimum Kvco/M, 0.06 MHz/V, for component calculations. Table 3-7shows the values we use in our design. Table 3-7. CP/LPF design values Icp
10µA R 157 k Cp 255pF C2 16pF Since the CP/LPF design decides the functional correctness of a PLL design, wrong calculations can almost certainly guarantee the failure of a design. Thus, we decided to use MATLAB Simulink to verify the correctness of the loop filter design. Simulink allows us to create a mathematical model for the system and simulate the system's behavior. The simulation speed is incredibly fast compared to Spice simulation. Better yet, it comes with a generic PLL model so that we can modify the model to suit our design needs. Figure 3-9 and Figure 3-10 show the modified PLL model we used in Simulink 26 and one of its output example, in which, we fr=1.0 MHz and fq=100MHz. With all four Kvco corner cases, which are shown in Table 3-4, being simulated, the proper choice of loop filter component values is verified. Now, we can continue with the circuit implementation.
Figure 3-9. MATLAB Simulink PLL model. Figure 3-10. Simulink simulation output for N=1000. 27 3.3.2 Design Implementation The hardest decision to make for the LPF implementation is what type of capacitor structure to use. In the process technology we are using, we have the options of using special Poly-Insulator-Poly (PiP) or Metal-Insulator-Metal (MiM) structure to build the high precision capacitors, or using MOS structure for area-efficient but substrate-noise-sensitive capacitors. Since the MOS capacitor structure gives 6 times more capacitance per area than the PiP/MiM structure for the same area, we decided to use it in our design. Furthermore, this leads to a more portable design since PiP/MiM structure is not available in some processes. To reduce the noise effects, we use the following techniques in the layout design: · place the capacitors as far away as possible from all digital units, including VCO and the PFD · place double guard-rings around the capacitor units · use dedicated analog power and ground supplies A MOS capacitor structure is shown in Figure 3-11. The overall capacitance is the gate capacitance when the MOS is turned on plus the parasitic capacitances that exist on the source and drain terminals. When the gate capacitance is substantially larger than parasitic capacitances, the overall capacitance can be approximated by C=CoxWL. Therefore, we want to construct the device with large gate length and small junction area. 28 Figure 3-11. MOS capacitor structure and its characteristic plot.
mo2 Cj
Voltage test_cap.tr0 t2 Cg MOS t1 Cj
0
0 2n 4n From the characteristic plot we see that the capacitance value remains constant once the device is on. HSpice simulation shows that the turn-on voltage is 1V for a PMOS device and 0.7V for a NMOS device. Due to the body effect, they are bigger than the devices' threshold voltages, as expected. Since the differential VCO control voltage ranges are 1.2-2.5V for Vctl+ and 0-1.3V for Vctl-, we use PMOS capacitors on the Vctl+ path and NMOS ones on the Vctl- path to ensure the devices are on during normal operation. For the charge pump unit, we use the design suggested in [Li00]. The complete schematic of the CP/LPF unit is shown in Figure 3-12 and the device sizes are listed in Table 3-8. In this design, transistors M1 to M12 form a charge pump, which takes differential input signals UP, UP/, DN, and DN/ from PFD units. Controlled by the input signals, transistors M9 to M12 act as current steering switches, deciding which of 4 charge-pump current paths are on. Since they don't draw much current, these four transistors are designed to be weak devices. Keeping them weak also helps reduce load on the input signals, which allows for faster switching times. The amount of current pumped in or drained out from the LPF units is regulated by the current mirror circuit formed by transistors M1 to M8, with the current source shown in Figure 3-13. The cur29 1 2 rent source circuit is a modified Vt-referenced self-biased cascode design, which has nice features such as power supply rejection and large voltage swing.
Figure 3-12. Differential CP/LPF unit. Vdd M1 Vbp1 Vdd M2 Gnd Gnd Vdd M13 Vctl+ DN M9 M3 Vbp2 M4 M10 UP 255pF Gnd I
cp Gnd 157K 16pF M14 Vdd Gnd M15 157K Vdd M11 M5 Vbn2 M6 Vdd M12 255pF DN/ 16pF Vctl- UP/ Vbn1 Vdd 281K U1 281K Vdd M16 Gnd M7 M8 + _ Gnd Gnd a_ref Table 3-8. Device sizes of CP/LPF unit. Devices m W ( µm ) L ( µm ) M1/M2 1 24 0.96 M3/M4 1 24 1.44 M5/M6 1 9.6 1.44 M7/M8 M9/M10 M11/M12 M13 M14 M15 M16 1 9.6 0.96 1 0.48 0.48 1 0.48 0.96 5 24 0.96 10 50 0.24 10 20 0.24 5 9.6 0.96 30 Figure 3-13. Current source for CP/LPF unit.
Vdd M5 M6 M8 50K Vbp1 M9 xn M10 M3 M4 M7 xbp2 Vbp2 xnt M15 M11 xpt M1 xp 40K M13 M2 I
css xbn2 M12 Vbn2 I cs M16 Vbn1 M14 Gnd Table 3-9. Device sizes of current source. Devices m W ( µm ) L ( µm ) M1/M2 1 30 0.96 M3/M4 1 6 1.44 M5/M6/M8 1 24 0.96 M7 1 24 1.44 M9/M10 1 75 0.96 M11/M12 1 2.4 1.44 M13/M14/M16 1 9.6 0.96 M15 1 9.6 1.44 Shown in Figure 3-13, the value of current Ics is given by
V TN I cs = I css = ---------- . R (3-9) For a current mirror system, we have
W W I out ---- = I REF ---- . L REF L out (3-10) Applying it to our design, as an example, we have Iout=Icp, IREF=Ics, Mout=M1/M3 in Figure 3-12, and MREF=M8/M7 in Figure 3-13. The relationship applies to each corresponding device pairs. By choosing the correct device size ratios, a 10 µA charge-pump current can be generated. 31 Continuing with the CP/LPF design, we see that a differential amplifier, U1, as well as two 281 kOhm resistors are also included in the design. They act as a common-mode feedback circuit to maintain the common mode voltage level of the differential output pair. The design schematic is shown in Figure 3-14. Large value resistors are used so that they won't draw current levels significant enough to alter the loop gain values. The final stages of the CP/LPF are two source-follower units. Their purpose is to shift the LPF output voltages to within the VCO control voltage range requirements, which are from 1.2V to 2.5V for Vctrl+ and from 0V to 1.3V for Vctrl-. The amount of voltage shift is equal to the Vgs of the device, which can be found by solving the equation
K W 2 - I d = ----- ---- ( V gs ­ V T ) ( 1 + V ds ) . 2 L (3-11) Figure 3-14. Common-mode feedback amplifier.
Vdd Vbp1 M1 Vbp2 M2 vip M3 M4 vin vop M5 Vbn2 M6 M7 M8 Gnd Gnd Table 3-10. Device sizes for common-mode feedback amplifier. Devices m W ( µm ) L ( µm ) M1 1 40 0.96 M2 1 40 1.44 M3/M4 24 9.6 0.96 M5/M6 1 9.6 1.44 M7/M8 1 9.6 0.96 32 3.4 Phase-Frequency Detector
Since the PFD update rate is 1.0MHz, which is in the low frequency range, the circuit implementation of the functional block shown in Figure 2-3 is rather straightforward. The design we use is from [Maneatis96] with adde