.
Transmission
14
2.
Chip
Layout
&
Extraction
15
A.
Layout
15
B.
Ground
Connection 16
C. Extraction







18
III.
Simulation
&
Experimental
Results
18
1.
Simulation
&
Chip
Testing
Plan
18
2. Results









19
A.
Regulator
Results
20
B.
Bandgap
Results
21
IV.
Assessment
of
Results 23
1.
Regulator
Behavior 23
2.
Bandgap
Behavior 24
V.
Conclusions








25
VI.
Future
Work
26 3
I. Introduction

Wireless sensor chips have many applications including biomedical monitoring, distributed
sensors within civil infrastructure and for sensors implanted within the body. Wireless
communication and powering of sensors has been accomplished in small modules, but not
completely on chip as traditional power sources are too large and bulky. One approach to a
chip sized wireless power source is a telemetry system to power the sensor. Wireless telemetry
systems require the use of an antenna which will inductively couple power onto the chip.

Previous work in this field includes that done by Huang et. al [1], Marschner et. al [2] and
Schuylenbergh & Puers [3]. Marschner separates the transmitter and energy reception into two
different off-chip antennas. Huang and Schuylenbergh & Puers both condense their design to
use only one antenna, but in both cases they are still off-chip and the frequency of operation is
very low. At high enough frequencies the antenna length requirement decreases, enabling it to
be placed entirely on chip. This section of the paper contains the design and test of a circuit to
be used at these very high frequencies with all on-chip components. Circuit simulation was done
through spectre with layout and fabrication through the spring 2002 and beginning of fall 2002
semesters. Fabrication was completed in February 2003, with chip characterization completed
by summer 2003. The results showed a constant regulated voltage output that was higher than
expected due to process variations. The bandgap circuit showed a constant voltage output that
matched simulation data, though the startup voltage necessary to obtain this functionality was
higher than expected. Future work includes using high breakdown voltage transistors as well as
larger transistors and capacitors for operation at both low and high input voltages. 4
II. Circuit Design

II.1 Overall Topology

The overall topology of the circuit is shown below in Figure 1. The rectifier provides the initial RF
to DC conversion and can provide a wide range of output voltages. However, this voltage output
is not stable and is very sensitive to the output load. The transmit block can either short or open
the antenna thru switch S
1
to either reflect or receive the RF signal respectively. The regulator
provides a constant DC power supply rail regardless of the sensor load.

Senso
r
Antenna

Figure 1. Overall Topology

II.1.A Rectifier Topology & Design


Figure 2. Rectifier Topology

The rectifier shown in Figure 2 is composed of a resonant loop to match and filter the input as
well as a decoupling capacitor and a voltage doubling rectifier. There is also a capacitor across 5
the rectifier to low-pass filter and smooth the rectified output. The tuning capacitor is sized to
resonate with the inductance of the antenna by using equation 1 where f is the frequency of
operation and L
antenna
and C
tune
are taken from Figure 2.

tune
antenna
C
L
f
*
1
2
=
{1}


C
clamp
and D
1
form the negative clamp while C
rect
and D
2
form the peak rectifier. The negative
clamp serves to raise the average sine wave voltage by preventing V
clamp
from going below
negative one diode drop (~-0.7 V). Thus, a sine wave at the input with an amplitude of 2 V
resulting from the LC resonator at V
A
would look like a sine wave with a range from -0.7 V to
3.3 V at V
clamp
. It should be noted that a sine wave with an amplitude less than -0.7 V would
never turn D
1
on, and thus would not be affected by the clamp circuit. The peak rectifier takes
this sine wave and converts it to a DC signal that is equal to the highest voltage minus one
diode drop. So, from the previous example the 2 V amplitude wave would have a resulting 2.6 V
rectified output. These signals can be seen below in Figure 3. It should again be noted that if the
input since wave has an amplitude less than 0.7 V, D
2
will never turn on and the voltage output
will be zero volts.


Figure 3. Rectifier Output Waveforms
6
Sizing of the clamp and rectifier capacitors takes into account the frequency of the input sine
wave and the load presented by the rest of the circuitry (regulator and sensor). This load, being
in parallel with the rectification capacitor forms an RC time constant of value R
load
* C
rect
. So, the
voltage at the output of the rectifier decreases slowly until the next peak, as can be seen in
Figure 4.

Figure 4. Rectifier Voltage due to Load

Thus, there will be a slight ripple at the output of the circuit and the average DC value will
decrease. The ripple can be minimized three different ways: 1) increase C
Rect
and thus increase
the time constant, 2) decrease the load (larger R
load
) by using low power devices, or 3) increase
the frequency of operation such that the period of the waveform is smaller. This third option has
the same effect as increasing the time constant. As the ripple peak-to-peak voltage gets larger,
the average value of the rectified output gets smaller and thus the regulator might not receive
enough voltage at its input to function properly. So, C
Rect
should be sized large enough for
whatever the application.

For this design, 1pF was chosen for C
Rect
. R
load
can be found by applying a DC voltage at the
output of the rectifier large enough to turn on the circuitry and measuring the current drawn. For
this design this value was 45 K leading to a time constant of 45 ns. This means that at a
frequency of 22 MHz the signal will have decreased to nearly 30% of its initial value. This is not
acceptable and a good rule of thumb is to operate at over four times this frequency where the 7
value has only decreased by 2%. For this design therefore, one should only operate above 88
MHz. For more details on the rectifier design, see pages 185 to 197 of [4].

II.1.A.i Rectifier Transistor Choice

The rectifier diodes are implemented as SiGe NPN transistors in the current design. Before
deciding the transistor sizing, a fundamental SiGe NPN transistor issue should be discussed.
For maximum unity gain frequency (f
T
), high frequency SiGe NPN transistors require a large
emitter current density. This is usually on the order of 1mA/
µm
2
. However, the maximum current
handling capacity of the transistor typically occurs very soon after the point of maximum f
T
. This
behavior can be seen in Figure 5, f
T
vs. emitter current for a hypothetical transistor with an
emitter area of 1
µm
2
, 50 GHz peak f
T
at a current density of 1mA/
µm
2
at peak fT and a
maximum current of 5mA. Actual data can be obtained from pages 100-106 of [5] for the 6HP
process and page 19 of [6] for the Jazz process and are not repeated here due to non
disclosure limitations.
0
10
20
30
40
50
60
1E-07
0.000001
0.00001
0.0001
0.001
0.01
Emitter Current
fT

Figure 5. Hypothetical f
T
vs. Emitter Current 8
Therefore, for maximum frequency of operation we should operate the transistors as close to
their maximum unity gain point as possible. If the load of the rectifier is well known, we may size
the transistors such that they yield a peak f
T
and the rectifier will be operable at very high
frequencies. If the load is unknown, the transistor should be sized large enough such that the
maximum current that can be delivered to the load does not exceed the transistors maximum
current handling capacity. The size of the capacitors does not affect this frequency dependency
because if the transistors cannot supply enough charge each cycle, the rectified voltage will
drop regardless of the charge capacity of the circuit.


II.1.B Regulator Topology & Design

The regulator shown in figure 6 was chosen for its high over-current protection and low internal
power dissipation. It is composed of a Bandgap voltage source to provide the reference voltage,
an Operational Amplifier to servo the Bandgap voltage (V
Ref
) to a resistor chain (V
X
), and a
PMOS pass transistor to compensate for different loads. Sizing the resistor chain according to
equation 2 can give any value of V
D
necessary at the output of the regulator (and the entire RF-
DC converter), given that the rectified voltage will be higher than the final V
D
. If the OpAmp has
enough gain, the voltage V
Ref
will appear at V
X
. V
D
may be found by a voltage divider equation.
For this design a V
D
of 3.0 Volts was chosen.






+
=
+
=
2
1
f
Re
2
1
2
1
*
R
R
D
R
R
R
D
X
R
R
V
V
R
R
R
V
V

{2}
9
Bandgap
R
R1
R
R2
OpAmp
Q
Pass
V
Ref
V
X
+
V
C
-
V
G
+
V
D
-

Figure 6. Regulator

There is a fundamental tradeoff between the area of Q
Pass
and maximum available current. The
larger the transistor, the more current it can source without driving the OpAmp output into a non-
linear region. Equation 3 shows the relationship between the current and the voltage from gate
to source (V
GS
).

(
) (
)
C
D
T
GS
ox
n
D
V
V
V
V
L
WC
i *
2
µ

{3}

As the current increases, the voltage from gate to source increases. Since the source is at a
fixed potential the gate