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Design of Indirect Power Factor Correction Using DSP56F80X MOTOROLA
Semiconductor Application Note
Order by AN1919/D
(Motorola Order Number)
Rev. 1.0, 4/01
� Motorola, Inc., 2001
In
di
rect P
o
we
r Fa
cto
r
Co
rre
ction
Design of Indirect Power
Factor Correction Using
DSP56F80X
Indirect Power Factor Correction Application
Design based on Motorola Software
Development Kit
1.
Introduction
This document describes the design of an Indirect Power
Factor Correction (Indirect PFC) application. It is based on
Motorolas 56F803/805 Digital Signal Processor (DSP),
dedicated to motor control applications.
Most practical electronic power supplies consist of a
conventional, single-phase, full-bridge rectifier, and filter
stages. Already well-established, this type of circuit draws
high current levels from the power line, producing a high
level of harmonics. This harmonic distortion and low power
factor (PF) reduces the maximum power available from
power lines, thereby decreasing the efficiency of the
electrical power grid. The European Normative EN
61000-3-2 defines the limits of the harmonic content of the
input current for the power line supplied equipment. To meet
these requirements, new designs require the use of an active
power factor correction (PFC) at the input. The PFC emulates
the ideal ohmic load through electronically controlled input
current drawn from the line.
There are many specific integrated circuits (IC) available on
the market to perform a PFC task. However, to perform the
PFC task, additional electronic components increasing the
system cost and complexity are required. Alternatively, there
is a way to implement the PFC control through the DSP in
addition to the main control tasks such as motor control. The
use of a digital PFC replaces a number of ICs, reducing
system cost. Another benefit of the software implementation
is the possibility of easy modification without changing the
hardware.
Contents
1. Introduction ................................... 1
2. Motorola DSP Advantage
and Features ............................. 2
3. Power Factor Correction Theory... 3
4. System Design Concept ................ 5
5. Hardware Implementation............. 8
5.1 System Outline ............................... 8
5.2 High Voltage Hardware Set............ 8
6. Software Design ............................ 9
6.1 Reference Voltage Calculation ....... 9
6.2 Milestone Generation.................... 10
6.3 State Diagram ............................... 11
6.3.1
Application State Machine ....... 11
7. SDK Implementation .................. 12
7.1 Files .............................................. 12
7.2 Drivers and Library Function ....... 13
7.3 Appconfig.h file............................ 13
7.4 PFC Control Constants ................. 14
7.5 PFC Control API .......................... 15
7.5.1
PFC_Init ................................... 15
7.5.2
PFC_SetUOut........................... 15
7.5.3
PFC_Enable.............................. 15
7.5.4
PFC_Disable ............................ 15
7.5.5
PC Master................................. 15
8. Memory Usage ............................ 16
9. References ................................... 16



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Indirect Power Factor Correction
Motorola DSP Advantage and Features
The indirect PFC design featured here satisfies the minimum DSP performance requirements. The
design is suitable for applications where the load of the DSP is high and the available resources are
low.
This application note presents the concept of the continuous conduction current mode boost power
factor corrector (PFC) with nominal output power of 180W. The PFC is digitally controlled by a
digital signal processor (DSP).
2.
Motorola DSP Advantage and Features
The Motorola DSP56F80x family is well suited for digital motor control, combining the calculation
capability of DSPs with MCUs controller features on a single chip. These DSPs offer a rich, dedicated
peripherals set like pulse-width-modulation (PWM) unit, analog-to-digital converter (ADC), Timers,
communication peripherals (SCI, SPI, CAN), on-board Flash, and RAM. Each family chip is well
suited for reliable motor control tasks.
A typical family member, the DSP56F805, provides the following peripheral blocks: Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and
four Fault inputs, fault tolerant design with dead-time insertion; supports both center- and
edge-aligned modes Two 12-bit Analog-to-Digital Converters (ADC) which support two simultaneous conversions;
ADC and PWM modules can be synchronized Two Quadrature Decoders each with four inputs or two additional Quad Timers Two General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with four
pins CAN 2.0 B Module with 2-pin port for transmit and receive Two Serial Communication Interfaces, each with two pins (or four additional GPIO lines) Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines) 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins Computer Operating Properly (COP) watchdog timer Two dedicated external interrupt pins External reset input pin for hardware reset External reset output pin for system reset JTAG/On-Chip Emulation (OnCE) module for unobtrusive, processor speed-independent
debugging Software-programmable, Phase Lock Loop-based frequency synthesizer for the DSP core clock Memory configuration
32252
�
16-bit words of program flash
512
�
16-bit words of program RAM
2K
�
16-bit words of data RAM
4K
�
16-bit words of data flash
2K
�
16-bit words of boot flash



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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
ARCHIVED BY FREESCALE SEMICONDUCT
OR,
INC.
2005 Power Factor Correction Theory
Indirect Power Factor Correction
3
3.
Power Factor Correction Theory
The main idea of the power factor correction algorithm is the input current waveform transformation to
be a sine signal having the same input voltage frequency. IEC standards do not require ideal sine
waveform for compatibility. It is enough to provide simple three-point approximation. In this case the
current waveform will be nearly rectangular. This simplification saves processor resources. The
hardware control of the inverter power switch is the next step of simplification. For this approach the
hardware provides instant value of the PFC input current. Thus, software controls the average value
only and does not have direct access to the inverter switch. See
Figure 3-1
.
Figure 3-1 System Concept
The system is designed to provide power supply with maximum 180W power. The system
incorporates the following hardware circuits:
~115-230V
50/60Hz
= 360V
external pulse width modulator
load
Zero crossing
detection
Pulse width
modulation
Inhibit
output
Output voltage
measurement
Base
frequency
Input
frequency
measurement.
Milestone
generation.
Reference
voltage
calculation
DSP56F80X
D
L
T
C
D
Zero crossing
detection
measurement
V
re
f
&



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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
.
.
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
ARCHIVED BY FREESCALE SEMICONDUCT
OR,
INC.
2005 4
Indirect Power Factor Correction
Power Factor Correction Theory Power supply rectifier Boost in