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T13/D98109R2

Ultra ATA Implementation Guide

To: T13 Technical committee

From: Mark
Evans

Quantum
Corporation

500
McCarthy Boulevard

Milpitas, 
CA  USA  95035

Phone: 
408-894-4019

Fax: 
408-952-3620

Email: 
mark.evans@quantum.com

Date: 07
December 1998

Subj: Ultra ATA implementation guide

Introduction:  The following proposal is for a new annex
for the ATA/ATAPI-5 standard.  This annex is intended to provide
details for implementation for Ultra ATA modes 0, 1, 2, 3, and 4 having
maximum transfer rates from 16.7 through 66.7 megabytes per second.

Clarification
of some aspects of the protocol and details not specifically stated
in the standard has been included for the benefit of component, PCB,
and device driver engineers.  This annex is not intended to be
comprehensive but rather informative on subjects that have caused design
questions.  Included are warnings about proper interpretation of
protocol where interpretation errors seem possible.

 

Table of Contents

 

Table of Figures

 

X.1 Signal Integrity

The evolution
of Ultra DMA has continued the trend of speed increases on the ATA interface
to match increases in disk drive performance.  The Ultra DMA modes
defined in this standard are:

Mode

Maximum transfer rate

0

16.67 megabytes
per second

1

22.22 megabytes
per second

2

33.33 megabytes
per second

3

44.44 megabytes
per second

4

66.66 megabytes
per second

Ultra DMA features
such as increased frequencies, double-edged clocking, and non-interlocked
signaling require improved signal integrity on the bus relative to that
required by PIO and Multiword DMA modes.  For Ultra DMA modes 0,
1 and 2 this is achieved by the use of partial series termination and
controlled slew rates.  For modes 3 and 4 an 80-conductor cable
assembly is required.  This cable assembly has ground lines interspersed
between all signal lines on the bus in order to control impedance and
reduce crosstalk, eliminating many of the signal integrity problems
inherent to the 40-conductor cable assembly.  However, many of
the design considerations and measurement techniques required for the
80-conductor cable assembly are different from those used for the 40-conductor
assembly.  Hosts and devices intended to be compatible with both
cable assembly types must be designed to meet all requirements for operation
with both assembly types.

For operation
in Ultra DMA modes 0, 1 and 2 with a 40-conductor cable assembly, concerns
include (in order of importance):  crosstalk between signals, ringing,
and timing.

For operation
in Ultra DMA modes 3 and 4 with an 80-conductor cable assembly, major
concerns are:  timing and ground bounce

Two of the features
Ultra DMA introduced to the ATA bus are double edged clocking and non-interlocked
(a.k.a. source-synchronous) signaling.  Double-edged clocking allows
a word of data to be transferred on each edge of the strobe signal,
resulting in doubling the data rate without increasing the fundamental
frequency of signaling on the bus.  Non-interlocked signaling means
that DATA and STROBE are both generated by the sender during a data
transfer.  In addition to previous signal integrity issues such
as double clocking on strobes due to ringing and delay-limited interlock
timings on the bus, this makes settling time and skew between different
signals on the bus very important for Ultra DMA operation.

X.1.1 Ringing and Data Settling Time

High amplitude
ringing can occur for some data patterns in systems using the 40-conductor
cable assembly.  The sixteen signal lines forming the data bus
of the ATA cable have only two ground lines adjacent to them (one on
each side of the data signals), and only seven ground lines are present
in the entire cable assembly.  This lack of ground return paths
has three negative effects on data signal integrity: 

Crosstalk between data lines is very high due
to inductive coupling.
Center conductors of the data bus exhibit very high inductance because
the distance from these signal lines to the current return path is large
and the ground return path is shared with many other signal lines.
Center conductors of the data bus are shielded from ground by the
other data lines around them.  When these lines are switching in
the same direction there is no potential difference and therefore no
effective capacitance between lines.

This combination
of factors results in the impedance of the center data lines rising
from the 110 to 150 ohms (as measured when the signals are not being
switched) to an almost purely inductive 300 to 600 ohms under some switching
conditions.  This value may vary widely based on cable length,
loading, and distance from chassis ground. 

In a simplified
model the 40-conductor cable assembly can be described as a pure inductor,
forming a series RLC resonant circuit with the capacitance of the IC
and PCB traces, and the combined resistance of the driver source impedance
and source series termination resistor.  The voltage across C will
ring sinusoidally in response to an input pulse at V_source, exponentially
decaying over time towards a steady state value.  The approximate
frequency of the ringing can be calculated as F = (1/(2*pi*sqrt(LC))). 
The rate of decay is proportional to R/L.