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SEQUOIA ESD SEQUOIA Design Systems, Inc.

SEQUOIA Design System, Inc.
137 Chapman Rd, Woodside, CA 94062, USA
phone: (650) 529 1704, fax: (707) 248 5652
email: info@SequoiaDesignSystems.com
Copyright © 2001
OVERVIEW
Increasing parasitic bipolar trigger volt-
age is an effective way to protect a frag-
ile output buffer from ESD damage by
making sure the main ESD protection
device triggers first. A cascode configu-
ration of two MOSFETs in series as
shown in Fig. 1 provides one solution to
this problem [1].
SEQUOIA Design Systems ESD soft-
ware was used to analyze the perfor-
mance of the fully isolated cascoded
structure.
MOSFETS
0.18
µ
m devices for this study were cre-
ated using SEQUOIA Device Designer
software (Fig. 2). Complete parametriza-
tion of device geometry, doping and
finite-element triangulation assures
ease-of-use. Excellent agreement
between simulation and
Transmission Line Pulse
(TLP) measured data was
achieved without any
adjustments to physical
coefficients (Figs. 3, 6).
High current behavior is
particularly important for
an ESD protection device
since much of device oper-
ation during an ESD event
is in this regime. Simula-
tion results match experi-
mental data for all regions
of the current-voltage
curve.
The MOSFET enters
breakdown at about 7V.
The goal of the cascode configuration is
to increase the trigger voltage of the par-
asitic bipolar to make sure it is higher
than the trigger voltage of a typical
grounded-gate MOSFET ESD protec-
tion device.
TEST CIRCUIT
A mixed-mode test circuit (Fig. 1) was
set up for the analysis of the cascoded
structure. Voltage waveforms and cur-
rents were extracted during the transient
simulation. One possible degree of
design freedom for the cascode is the
gate bias Vg applied to the upper MOS-
FET. Resistors R3, R4 were used to set
the gate bias to either a fixed value or tie
it to IO pad potential.
RESULTS
The cascode was subjected to a 2000V
Human Body Model (HBM) pulse. The
gate of the upper MOSFET was first tied
to IO pad potential. Voltage waveforms
Fig. 1
Fig. 2
Fig. 3
SEQUOIA ESD
Cascoded NMOS Output Buffer Design
A p p N o t e 2 0 0 1 E S D 0 2 SEQUOIA Design System, Inc.
137 Chapman Rd, Woodside, CA 94062, USA
phone: (650) 529 1704, fax: (707) 248 5652
email: info@SequoiaDesignSystems.com
Cascoded NMOS Output Buffer Design, AppNote 2001ESD02
on the two MOSFETs, as well as the out-
put voltage, demonstrate that the overall
trigger voltage is in fact increased signif-
icantly from 7V to about 13V. The VSS
device M0 triggers first, followed by
device M1 with some delay during
which the voltage across device M1 is
building up to its breakdown value of 7V.
Since at this time device M0 is already in
snapback-mode, the voltage drop across
M0 is smaller than its breakdown voltage
of 7V (Fig. 4).
Further increase of the the trigger volt-
age of the fully isolated cascode is pos-
sible by reducing the gate bias Vg of the
upper MOSFET. This is due to an
increase in breakdown voltage of the
upper MOSFET at lower gate biases.
Current-voltage curves extracted from
the transient simulation of the cascode
for different gate biases Vg are shown in
Fig. 5. In all cases the overall trigger
voltage is substantially higher than the
trigger voltage of a single MOSFET
(7V).
The behavior of the cascode is signifi-
cantly different for Vg<7.5V from that
for higher gate biases. Overall trigger
voltages as high as 17V are achieved at
low Vg, when the upper MOSFET is
turned off up to its breakdown. For high
Vg values, the upper transistor M1 con-
ducts significant current starting at
breakdown of the lower MOSFET M0
and the overall breakdown voltages are
lower at about 13V.
The lowered trigger voltage at higher
gate biases is due to a reduction in break-
down voltage of the upper MOSFET, as
shown by a set of breakdown curves for
a range of gate biases (Fig. 6).
These results are valid for the fully iso-
lated cascode structure. A different opti-
mum choice for the gate bias was
reported for the case of minimum spac-
ing between M0 and M1 due to coupling
between the devices [1].
SUMMARY
Cascoding MOSFETs can be an effective
way to increase the trigger voltage of the
parasitic bipolar device and help protect
fragile NMOS output buffer devices.
SEQUOIA ESD offers a complete inte-
grated software solution for the analysis
and design of ESD protection circuits.
Physical accuracy and ease-of-use are
provided in a uniquely powerful pack-
age. For more information please contact
SEQUOIA Design Systems.
REFERENCES
[1] J.W. Miller, M.G. Khazhinsky, J.C.
Weldon, Engineering the Cascoded
NMOS Output Buffer for Maxi-
mum Vt1, EOS/ESD 2000, pp. 308-
317.
M0
M1
low Vg
high Vg
Vg
Fig. 4
Fig. 5
Fig. 6