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MODELING AND CHARACTERIZATION OF SUBSTRATE RESISTANCE FOR DEEP SUBMICRON ESD PROTECTION DEVICES MODELING AND CHARACTERIZATION
OF SUBSTRATE RESISTANCE
FOR DEEP SUBMICRON ESD PROTECTION DEVICES
A DISSERTATION
SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING
AND THE COMMITTEE ON GRADUATE STUDIES
OF STANFORD UNIVERSITY
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
XIN YI ZHANG
AUGUST 2002 ii

C
Copyright by Xin Yi Zhang 2002
All rights Reserved iv
ABSTRACT
As device dimensions continue to shrink, higher current densities and lower voltage
tolerances make ESD, or Electrostatic Discharge, an increasingly important issue to
guard against for ensuring reliability. Industry data show that one-third of all customer
returns are due to ESD.
IC chips are protected against ESD by on-chip protection circuits, which are
connected between the I/O pads and the internal circuitry. The protection circuit, which
consists of protection devices, is designed to rapidly discharge high current in an ESD
event.
Typically, the design of ESD protection circuits is an empirical approach. Several
candidate circuits are fabricated, characterized, and evaluated for key physical and
performance parameters using known testing techniques. Different combinations of
device geometries and process technologies are evaluated until a suitable circuit with the
desired characteristics is found. This resource intensive design approach clearly
motivates a simulation based solution which enables quicker turnaround as well as
obvious cost-savings in materials and resources. v
The focus of our research is on modeling and characterizing ESD protection
devices, especially the substrate resistance, in a state-of-art CMOS technology. Unlike
normal MOS operation, both the channel and the substrate region in a given device need
to be modeled to show that current extends from the channel into the substrate under ESD
stress. We begin by developing a circuit model to simulate the high current characteristics
under ESD stress since none exist in commercial circuit simulators. We then demonstrate
the extraction of circuit-level parameters from experimental data using a systematic
extraction methodology.
The next phase of our research extends the circuit model to enable simulation of
different layout and process variations by focusing on modeling substrate resistance.
Substrate resistance determines the on/off state of the protection device by providing
current discharge paths from drain to substrate and drain to source. This parameter also
captures the substrate interactions of different protection circuit elements.
In order to address the sensitivity of substrate resistance to layout and process varia-
tions, we propose a new methodology called quasi-mixed-mode (QMM) device and cir-
cuit simulation approach, and we will describe the QMM approach in detail as well as
illustrate the application of the model to the modeling of substrate resistance for deep sub-
micron ESD protection nMOSFETs. The substrate resistance simulated by this method
shows good agreement with the values extracted from experimental data. This technique
can be employed to simulate turn-on characteristics of ESD protection devices and deter-
mine the impact of process and layout variations on their reliability before fabrication of
the actual devices. vi
ACKNOWLEDGMENTS
I would not have finished this thesis without the help and encouragement from a
number of individuals. First, I would like to thank my advisor, Professor Robert Dutton.
He introduced me to the subject of ESD circuit and device modeling. He steered me
towards the idea to use numerical simulation to solve layout dependent ESD modeling
problems. I learnt to treasure the free and cooperative work environment that Bob fosters
among his students.
I also had the good fortune of working with people who are leaders in the field of
ESD device design, modeling, and characterization. Drs. Julian Chen and Tom Vrotsos
offered me a summer job at Texas Instruments, giving me an opportunity to study the ESD
problem at the industry level. While there at TI, I was lucky to have met Dr. Ajith Amer-
askera, Dr. Charvaka Duvvury, Dr. Shridar Ramaswamy, and Gupta Vikas. They, espe-
cially Ajith, have helped me tremendously with my research by letting me take
measurements of their test structures and helping me to analyze the resulting data.
Dr. Stephen Beebe, who was also Bobs student and also did his dissertation on ESD
modeling, directed me into ESD work at Advanced Micro Devices. While at AMD, I
learned how to effectively apply device simulation to analyze ESD problems.
Dr. Tim Maloney from Intel also gave me valuable feedbacks on my research. vii
I wrote more than half of my thesis while working full time at Marvell Semiconduc-
tor Technology. This exciting job provided me with important insights into the interactions
between the protection and protected elements. I want to thank Dr. Joe Li for all the help-
ful discussions and ideas on ESD protection. I also want to thank Drs. Eric Minami and
Leechung Yiu for all their support and encouragement.
Of course, none of this would have been possible without the generous financial sup-
port from Semiconductor Research Corporation. I am very grateful to SRC for giving me
this great opportunity to carry out my research.
My years at Stanford has been wonderful. Special thanks go to Dr. Zhiping Yu, not
only for his many lectures on device physics but also for his advice on life in general.
Kaustav Banerjee, who is my co-author, helped me a lot by going over my results and
proof-reading my paper. I would also like to thank my orals and reading committee: Drs.
Robert Dutton, Bruce Wooley, Kenneth Goodson, Zhiping Yu, and Kunle Olukotun. In
addition, I want to thank the whole TCAD group, specifically my officemates Edward,
Francis, Zak, Choshu, Jaejung, Ken, Tao, Nathan, and Michael for all the discussions and
support over the years. Without Dan Yergeau answering and solving all my Unix questions
and problems, I would be still working on my thesis. Fely, Miho, and Maria also made my
life easier by providing all the administrative support, especially for Felys friendship and
guidance on navigating through all the deadlines during my graduate career.
Last but certainly not the least, I would like to thank all my friends who made my
bad days bearable and good days wonderful at Stanford, especially Marianna Landa for
tirelessly proof-reading my thesis, polishing all the rough sentences, and Jeff for his ever-
lasting support and encouragement, and of course Mom, Dad, and Frankie who have
always encouraged me during these many years of study.
This thesis is dedicated to my grandparents. viii
CONTENTS
Abstract
iv
Acknowledgments
vi
List of Tables
xi
List of Figures
xii
1
Introduction
1
1.1
ESD and ESD Protection in the Semiconductor Industry . . . . . . . . . . . . 1
1.2
The Importance of Modeling ESD Protection Circuits and Devices. . . . 4
1.3
Previous Studies of the ESD Model and Existing Simulation Tools . . . . 7
1.4
Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
ESD Device Characterization and Compact Model
11
2.1
Types of ESD Stress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2
Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3
Compact Model for Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4
Modeling of I
gen
and M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ix
2.5
Extraction Methodology for M parameters . . . . . . . . . . . . . . . . . . . . . . 27
2.6
Substrate Resistance Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.7
Extraction of Rsub Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.8
Parasitic Bipolar Transistor Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.9
Extraction of
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.10 High Current ESD Compact Model Implementation . . . . . . . . . . . . . . 51
2.11 Impacts of Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3
The Substrate Resistance Model: The Quasi-Mixed-Mode
Methodology
60
3.1
R
sub
Model Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.2
The QMM Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3
Verification of Simplified Device Simulation . . . . . . . . . . . . . . . . . . . . 71
3.4
QMM Method vs. Full Device Simulation . . . . . . . . . . . . . . . . . . . . . . 77
3.5
Discussion of the QMM Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4
Calibration and Simulation of Substrate Resistance Using the
QMM Methodology
89
4.1
Calibration and Simulation of Substrate Resistance for Single
Finger Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.2
Effects of Layout and Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.3
Motivation for 3D substrate Resistance Model . . . . . . . . . . . . . . . . . . 103
4.4