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SESSION SESSION NUMBER TITLE TUESDAY 1. Products & Dielectrics 2A Dielectrics 2B Compound Devices 1 2C SESSION
SESSION
NUMBER
TITLE
TUESDAY
1.
Products & Dielectrics
2A
Dielectrics
2B
Compound Devices 1
2C
Interconnect
2D
ESD/Latchup
WEDNESDAY
3A
High k 1
3B
SER
3C
Assembly & Packaging
3D
Products & Circuits 1
3E
Products & Circuits 2
4A
High k 2
4B
High Voltage Device
4C
Process Integration Reliability
4D
MEMS
4E Memory
1
THURSDAY
5A
Transistors
5B
BEOL
5C
Compound Devices 2
5D
Memory 2
5E
Product & Circuits 3
6A
Failure Analysis
WEDNESDAY POSTERS
AP
Assembly & Packaging
CD
Compound Devices
DI
Dielectrics
ES
ESD
FA
Failure Analysis
HK
High k
IT
Interconnect
MY
Memory
PC
Product & Circuits
PI
Process Integration Reliability
SE
SER
TR
Transistors 2
Jan. 26, 2006
T
ECHNICAL
P
ROGRAM
Tuesday, March 28, 8:00 a.m., Room A, Plenary Session
Symposium OpeningCarole Graas, General Chair
Keynote address: Adaptation of Reliability Methodologies to
Market Expectations and Technology Roadmaps, by Timothy
Collopy, Director of Quality, IBM Systems & Technology Group
2005 IRPS Best/Outstanding Paper and Best Poster Awards
Ed Cole Jr., 2005 IRPS Technical Program Chair
Jewel recovery from past IRPSR.C. Blish II, Advanced Micro
Devices, Inc./R.W. Thomas, Technical Experts Network
Technical Program IntroductionJohn Suehle, Technical Program
Chair
Tuesday, March 28, 10:30 a.m., Room A, Plenary Session
1. PRODUCTS & DIELECTRICS
Co-Chairs: Robert Kwasnick, Intel and Ben Kaczer, IMEC
1.1
PREDICTION OF LOGIC PRODUCT FAILURE DUE TO THIN-
GATE OXIDE BREAKDOWNY.-H. Lee, N. Mielke, M.
Agostinelli, S. Gupta, R. Lu, and W. McMahon, Intel, Santa Clara,
CA
Models for predicting the oxide-breakdown reliability of high performance
CPU logic products are developed from capacitor TDDB data and matched
to actual failure rates in high-voltage lifetest. Such a calibration exercise
is crucial for accurate reliability estimation. Once calibrated, a model is
useful for assessing changes in use conditions or circuit design.
1.2
RECOVERY EFFECTS IN THE DISTRIBUTED CYCLING OF
FLASH MEMORIESN. Mielke, H.P. Belgal, A. Fazio, and Q.
Meng, Intel, Santa Clara, CA
Damage from program/erase cycling partially recovers between cycles.
The effect is temperature accelerated with an activation energy of 1.1eV.
Between-cycle delays dramatically extend retention lifetime for the charge-
detrapping mechanism. An accelerated reliability model is proposed which
comprehends cycle count, cycle rate, cycling temperature, retention time,
and retention temperature.
1.3
POST-BREAKDOWN CHARACTERISTICS OF EXTRINSIC
FAILURE MODE FOR ULTRA-THIN GATE OXIDESE. Wu,
IBM, Essex Jct., VT/J. Sune, Univ. Autònoma de Barcelona,
Bellaterra, Spain
Post-breakdown properties of extrinsic failure mode are thoroughly
investigated in comparison with intrinsic mode. We show that regardless
of first BD modes or how the percolation path is initiated, post-breakdown
characteristics of intrinsic and extrinsic BD modes are essentially identical,
thus suggesting that the same mechanism controls the post-BD phase.
This important finding indicates that the post-BD methodology developed
for intrinsic BD mode can also be applied to extrinsic BD mode methodology
in circuit reliability modeling. A burn-in methodology is developed to take
into account of gate oxide reliability in post-breakdown phase.
1.4
A COMPREHENSIVE STUDY OF LOW-k SiCOH TDDB
PHENOMENA AND ITS RELIABILITY MODEL
DEVELOPMENTF. Chen, O. Bravo, K. Chanda, P. McLaughlin,
T. Sullivan, J. Gill, J. Lloyd, E. Wu, R. Kontra, and J. Aitken,
IBM, Essex Jct., VT
The TDDB degradation of CVD low-k dielectric at 65nm technology
node under both static and dynamic bias-temperature stresses over a
wide range of fields and temperatures were critically studied. Interrelation
of field and temperature dependence between TDDB thermal activation
energy and field acceleration parameter was identified. Based on the
extensive long-term TDDB (longer than 9 months) test results, a new
field-acceleration model: ?E model, was developed for reliability lifetime
projection with the assumption of unchanged leakage conduction
mechanism at use conditions.
Tuesday, March 28, 2:00 p.m., Room A,
Parallel Session
2A DIELECTRICS
Co-Chairs: Ben Kaczer, IMEC and
Tanya Nigam, Cypress Semiconductor
2A.1 VOLTAGE SCALING AND STATISTICAL PROPERTIES OF
POST-BREAKDOWN FOR ULTRA-THIN-OXIDE PFETS IN
INVERSION MODEE. Wu, IBM, Essex Jct., VT/J. Sune, Univ.
Autònoma de Barcelona, Bellaterra, Spain
We report an extensive study of voltage scaling and statistic properties
of post-breakdown for ultra-thin-oxide PFETs in inversion mode. We
demonstrate that both the first BD and time-to-circuit-failure
distributions follow Poisson area scaling even though the TFAIL
distributions are non-Weibull. Unlike NFET inversion, which is dominated
by a singe-spot progressive BD mode, multiple competing progressive
BD spots are found to dominate the post-BD phase in PFET inversion
case. The voltage acceleration of TBD(1st) and TRES are found to be
similar, also due to the role of competing BD spots.
2A.2 PRECISE AND SIMPLE METHOD FOR DETECTION OF
INITIAL DEFECTS IN 1.2 nm GATE DIELECTRICS BASED
ON NONLINEAR CONDUCTIONSH. Suto, T. Muratomi, K.
Ebihara, M. Kanno, T. Gocho, and N. Nagashima, Sony Corp.,
Atsugi-shi Kanagawa, Japan
A precise method to detect initial defects on gate dielectrics is proposed.
This method proved to be a powerful tool for choosing the best process
conditions to suppress initial defects and predicting the reliabilities.
Detailed studies of the gate leakage currents through initial defects and
breakdown spots are also discussed.
2A.3 A COMPREHENSIVE STUDY OF FN DEGRADATION FOR
DRIVER MOSFETs IN NONVOLATILE MEMORY CIRCUIT
H. Aono, E. Murakami, T. Mizuno, H. Sato, K. Haraguchi, M.
Kato, and K. Kubota, Renesas Technology Corp., Ibaraki, Japan
A degradation mode by FN stress is investigated comprehensively . We
demonstrate that this degradation really occurs in driver MOSFETs in
actual circuits after E/W operation. We also exhibit that this degradation
has strong correlation with total injected gate and substrate current and
propose a hot-hole induceddegradation mechanism.
2A.4 VOLTAGE ACCELERATION OF TBD AND ITS
CORRELATION TO THE POST BREAKDOWN
CONDUCTIVITY OF N- AND P-CHANNEL MOSFETsM.
Rohner, A. Kerber, and M. Kerber, Infineon Technologies, Munich,
Germany
The gate oxide breakdown behaviour of advanced n- and p-channel CMOS
devices was thoroughly investigated from the time range of electrical
overstress events (µs) to package level test conditions (106 s). The voltage
acceleration follows the power-law-model over 12 decades in time. In
addition the current -voltage driven wear out was studied for linear and
non-linear driver elements. It was found that the evolution of the post
breakdown conductivity strongly depends on the current limitation and
the associated voltage drop across the driving stage. The post breakdown
evolution can be described by the voltage acceleration.
2A.5 EXPLAINING VOLTAGE-DRIVEN BREAKDOWN
STATISTICS BY ACCURATELY MODELING LEAKAGE
CURRENT INCREASE IN THIN SiON AND SiO
2
/HIGH-k
STACKSR. Degraeve, P. Roussel, M. Cho, T. Kauerauf, B.
Kaczer, and G. Groeseneken, IMEC, Leuven, Belgium
The properties of the hard BD distribution in the presence of a digital soft
BD are demonstrated. We show how information on the digital soft BD
distribution can be extracted from the leakage current increase preceding 3
Jan. 26, 2006
the hard BD. By generalizing this interpretation the time dependence of
conventional stress-induced leakage current (SILC) in ultra-thin dielectrics
is analytically modeled.
Tuesday, March 28, 4:30 p.m., Room A, Parallel Session
2B COMPOUND DEVICES 1
Co-Chairs: Robert S. Okojie, NASA-Glenn Research Center and
Brian J. Skromme, Arizona State University
2B.1 (invited) EFFECTS OF DISLOCATIONS AND STACKING
FAULTS ON THE RELIABILITY OF SiC PiN DIODESR.E.
Stahlbush, K.X. Liu, and M.E. Twigg, Office of Naval Research,
Washington, D.C.
Compared to silicon, SiC has a larger bandgap, higher breakdown field
and higher thermal conductivity making superior power devices possible.
A major problem impeding reliable PiN diodes is stacking faults (SF)
formation during operation. The origins of the SFs, their electrical
effect, and progress to reduce SFs will be discussed.
2B.2 GaN-ON-Si FAILURE MECHANISMS AND RELIABILITY
IMPROVEMENTSS. Singhal, J.C. Roberts, P. Rajagopal, T. Li,
A.W. Hanson, B. Therrien, J.W. Johnson, I.C. Kizilyalli, K.J.
Linthicum, Nitronex Corp., Raleigh, NC
Highlights of a DC reliability data set are presented and failure analysis
is perfomed on degraded devices. The results reveal a permanent Schotkky
Barrier Height (SBH) shift. A gate anneal