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8-bit Microcontroller with 16K Bytes of In-System Programmable Flash ATmega161 ATmega161L 1
Features High-performance, Low-power AVR
®
8-bit Microcontroller Advanced RISC Architecture
130 Powerful Instructions Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 8 MIPS Throughput at 8 MHz
On-chip 2-cycle Multiplier Program and Data Memories
16K Bytes of Non-volatile In-System Programmable Flash Endurance: 1,000
Write/Erase Cycles
Optional Boot Code Memory with Independent Lock bits Self-programming of
Program and Data Memories
512 Bytes of Non-volatile In-System Programmable EEPROM Endurance: 100,000
Write/Erase Cycles
1K Byte of Internal SRAM
Programming Lock for Software Security Peripheral Features
Two 8-bit Timer/Counters with Separate Prescaler and PWM
Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare,
Capture Modes and Dual 8-, 9-, or 10-bit PWM
Dual Programmable Serial UARTs
Master/Slave SPI Serial Interface
Real-time Counter with Separate Oscillator
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator Special Microcontroller Features
Power-on Reset
External and Internal Interrupt Sources
Three Sleep Modes: Idle, Power-save and Power-down Power Comsumption at 4 MHz, 3.0V, 25
°C
Active 3.0 mA
Idle Mode 1.2 mA
Power-down Mode < 1 µA I/O and Packages
35 Programmable I/O Lines
40-lead PDIP and 44-lead TQFP Operating Voltages
2.7V - 5.5V for the ATmega161L
4.0V - 5.5V for the ATmega161 Speed Grades
0 - 4 MHz for the ATmega161L
0 - 8 MHz for the ATmega161 Commercial and Industrial Temperature Ranges
Disclaimer
Typical values contained in this data sheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology.
Min and Max values will be available after the device is characterized.
8-bit
Microcontroller
with 16K Bytes
of In-System
Programmable
Flash
ATmega161
ATmega161L
Note:
Not recommended in new
designs.
Rev. 1228DAVR02/07 2
ATmega161(L)
1228DAVR02/07
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
(OC0/T0) PB0
(OC2/T1) PB1
(RXD1/AIN0) PB2
(TXD1/AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
(RXD0) PD0
(TXD0) PD1
(INT0) PD2
(INT1) PD3
(TOSC1) PD4
(OC1A/TOSC2) PD5
(WR) PD6
(RD) PD7
XTAL2
XTAL1
GND
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE0 (ICP/INT2)
PE1 (ALE)
PE2 (OC1B)
PC7 (A15)
PC6 (A14)
PC5 (A13)
PC4 (A12)
PC3 (A11)
PC2 (A10)
PC1 (A9)
PC0 (A8)
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
(RXD0) PD0
NC*
(TXD0) PD1
(INT0) PD2
(INT1) PD3
(TOSC1) PD4
(OCIA/TOSC2) PD5
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE0 (ICP/INT2)
NC*
PE1 (ALE)
PE2 (OC1B)
PC7 (A15)
PC6 (A14)
PC5 (A13)
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
(WR) PD6
(RD) PD7
XT
AL2
XT
AL1
GND
NC*
(A8) PC0
(A9) PC1
(A10) PC2
(A11) PC3
(A12) PC4
PB4 (SS)
PB3 (TXD1/AIN1)
PB2 (RXD1/AIN0)
PB1 (OC2/T1)
PB0 (OC0/T0)
NC*
VCC
P
A0 (AD0)
P
A1 (AD1)
P
A2 (AD2)
PA3 (AD3)
* NC = Do not connect
(Can be used in future devices)
TQFP
PDIP 3
ATmega161(L)
1228DAVR02/07
Description
The ATmega161 is a low-power CMOS 8-bit microcontroller based on the AVR

RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega161
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed. The AVR

core combines a rich
instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in one single instruction executed in one clock cycle. The resulting architec-
ture is more code-efficient while achieving throughputs up to ten times faster than
conventional CISC microcontrollers.
The ATmega161 provides the following features: 16K bytes of In-System or Self-
programmable Flash, 512 bytes EEPROM, 1K byte of SRAM, 35 general purpose I/O
lines, 32 general purpose working registers, Real-time Counter, three flexible
Timer/Counters with Compare modes, internal and external interrupts, two programma-
ble serial UARTs, programmable Watchdog Timer with internal Oscillator, an SPI serial
port and three software-selectable power saving modes. The Idle mode stops the CPU
while allowing the SRAM, Timer/Counters, SPI port and interrupt system to continue
functioning. The Power-down mode saves the register and SRAM contents but freezes
the Oscillator, disabling all other chip functions until the next External Interrupt or Hard-
ware Reset. In Power-save mode, the timer Oscillator continues to run, allowing the
user to maintain a timer base while the rest of the device is sleeping.
The device is manufactured using Atmels high-density non-volatile memory technology.
The On-chip Flash Program memory can be reprogrammed using the Self-programming
capability through the Boot Block and an ISP through the SPI port, or by using a conven-
tional non-volatile Memory programmer. By combining an enhanced RISC 8-bit CPU
with In-System Programmable Flash on a monolithic chip, the Atmel ATmega161 is a
powerful microcontroller that provides a highly flexible and cost-effective solution to
many embedded control applications.
The ATmega161 AVR

is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, In-Cir-
cuit Emulators and evaluation kits. 4
ATmega161(L)
1228DAVR02/07
Block Diagram
Figure 1. The ATmega161 Block Diagram
PROGRAMMING
LOGIC
SPI
UARTS
PB0 - PB7
VCC
GND
+
-
ANALOG
COMP
ARA
TOR
8-BIT DATA BUS
DATA DIR.
REG. PORTA
DATA REGISTER
PORTA
PORTA DRIVERS
PA0-PA7
DATA DIR.
REG. PORTC
DATA REGISTER
PORTC
PORTC DRIVERS
PC0-PC7
PORTD DRIVERS
PD0 - PD7
DATA DIR.
REG. PORTD
DATA REGISTER
PORTB
PORTB DRIVERS
PORTE DRIVERS
PE0 - PE2
DATA REG.
PORTE
DATA DIR
REG. PORTE
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTERS
INSTRUCTION
DECODER
TIMING AND
CONTROL
OSCILLATOR
INTERRUPT
UNIT
EEPROM
STATUS
REGISTER
Z
Y
X
ALU
RESET
XTAL2
XTAL1
CONTROL
LINES
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD 5
ATmega161(L)
1228DAVR02/07
Pin Descriptions
VCC
Supply voltage.
GND
Ground.
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors
(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED dis-
plays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,
they will source current if the internal pull-up resistors are activated. The Port A pins are
tri-stated when a reset condition becomes active, even if the clock is not running.
Port A serves as a Multiplexed Address/Data port when using external memory
interface.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output
buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega161 as listed
on page 92.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output
buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port C also serves as an address high output when using external memory interface.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output
buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega161 as listed
on page 101.
Port E (PE2..PE0)
Port E is a 3-bit bi-directional I/O port with internal pull-up resistors. The Port E output
buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition bec