-
zation for operation, wordlength, latency, and interface.
Features Available for Virtex-II, Virtex-II Pro, Virtex-4,
Virtex-5, Spartan-3, Spartan-3E, and Spartan-3A
DSP FPGA family members Supported operators: multiply add/subtract divide square-root comparison conversion from floating-point to fixed-point conversion from fixed-point to floating-point conversion between floating-point types Compliance with IEEE-754 Standard (with only
minor documented deviations) Support for DSP48 on Virtex-4 FPGAs, DSP48E on
Virtex-5 FPGAs, and DSP48A on Spartan-3A DSP
FPGAs Parameterized fraction and exponent wordlengths Optimizations for speed and latency Fully synchronous design using a single clock For use with CORE Generator software which is
available in the Xilinx ISE 10.1 software
Overview
The Xilinx Floating-Point core allows a range of float-
ing-point arithmetic operations to be performed on
FPGAs. The operation is specified when the core is gen-
erated, and each variant has a common interface. This
interface is shown in
Figure 1
. When a user selects an
operation that requires only one operand, the B input is
omitted.
Floating-Point Operator v4.0
DS335 April 25, 2008
Product Specification
X-Ref Target - Figure 1
Figure 1: Block Diagram of Generic Floating-Point Binary Operator Core
Floating-Point
Operator
Resu lt = A o p B
A
B
OPERATION
OPERATION_ND
OPERATION_RFD
SCLR
CE
CLK
RESULT
UNDERFLOW
OVERFLOW
INVALID_OPERATION
DIVIDE_BY_ZERO
RDY
DS335_01_021508 Floating-Point Operator v4.0
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DS335 April 25, 2008
Product Specification
Functional Description
The floating-point and fixed-point representations employed by the core are described in
"Floating-
Point Number Representation"
and
"Fixed-Point Number Representation."
Floating-Point Number Representation
The core employs a floating-point representation that is a generalization of the IEEE-754 Standard to
allow for non-standard sizes
[Ref 1]
. When standard sizes are chosen, the format and special values
employed are identical to those described by the IEEE-754 Standard.
Two parameters have been adopted for the purposes of generalizing the format processed by the Float-
ing-Point core. These specify the total format width and the width of the fractional part. For standard
single precision types, the format width is 32 bits and fraction width 24 bits. In the following descrip-
tion, these widths are abbreviated to
and
, respectively.
A floating-point number is represented using a sign, exponent, and fraction (which are denoted as s,
E, and
, respectively).
The value of a floating-point number is given by:
The binary bits,
, have weighting
, where the most significant bit
is a constant 1. As such, the
combination is bounded such that
and the number is said to be normal-
ized. To provide increased dynamic range, this quantity is scaled by a positive or negative power of 2
(denoted here as E). The sign bit provides a value that is negative when
, and positive when
.
The binary representation of a floating-point number contains three fields as shown in
Figure 2
.
As
is a constant, only the fractional part is retained, that is,
. This requires only
bits. Of the remaining bits, one bit is used to represent the sign, and
bits represent
the exponent.
The exponent field, , employs a biased unsigned integer representation, whose value is given by:
The index, i, of each bit within the exponent field is given in
Figure 2
.
The signed value of the exponent, , is obtained by removing the bias, that is,
.
X-Ref Target - Figure 2
Figure 2: Bit Fields Within the Floating-Point Representation
w
w
f
b
0
.b
1
b
2
b
w
f
1 v
1 (
)
s
2
E
b
0
.b
1
b
2
b
w
f
1 =
b
i
2
i b
0
0
b0.b1b2bp 1 2
< s
1
=
s
0
=
f
e
s
3
w
f
-1
1
2
w
e
-1
0
Bit position
0
w
f
-2
w
f
-1
Bit significance (i)
w -1
w
w
f
-1
b
0
f
b
1
b
w
f
1 =
w
f
1 w
e
w
w
f =
e
e
e
i
2
i
i
0
=
w
e
1
=
E
E
e
2
w
e
1 1 (
) = DS335 April 25, 2008
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3
Product Specification
Floating-Point Operator v4.0
In reality,
is not the wordlength of the fraction, but the fraction with the hidden bit,
, included.
This terminology has been adopted to provide commonality with that used to describe fixed-point
parameters (as employed by Xilinx System Generator
TM
for DSP).
Special Values
A number of values for ,
and
have been reserved for representing special numbers, such as Not
a Number (NaN), Infinity (
)
, Zero (0), and denormalized numbers (see
"Denormalized Numbers"
for
an explanation of the latter). These special values are summarized in
Table 1
.
Note that in
Table 1
the sign bit is undefined when a result is a NaN. A NaN generated by the core sets
the sign to 1. Also, infinity and zero are signed. Where possible, the sign is handled in the same way as
finite non-zero numbers. For example,
,
and
. A mean-
ingless operation such as
raises an invalid operation exception and produces a NaN as a result.
IEEE-754 Support
The Xilinx Floating-Point core complies with much of the IEEE-754 Standard. The deviations generally
provide better trade-off of resources against functionality. Specifically, the core deviates in the follow-
ing ways: "Non-Standard Wordlengths" "Denormalized Numbers" "Rounding Modes" "Signalling and Quiet NaNs"
Non-Standard Wordlengths
The Xilinx Floating-Point core supports a greater range of fraction and exponent wordlength than
defined in the IEEE-754 Standard.
Standard formats commonly implemented by programmable processors: Single Format
- uses 32 bits, with a 24-bit fraction and 8-bit exponent. Double Format
- uses 64 bits, with 53-bit fraction and 11-bit exponent.
Less commonly implemented standard formats are: Single Extended
- wordlength extensions of 43 bits and above Double Extended
- wordlength extensions of 79 bits and above
Table 1: Special Values
Symbol for Special
Value
s Field
e Field
f Field
NaN
dont care
(that is,
)
Any non-zero field.
For results that are NaN the
most significant bit of fraction is
set (that is,
)
sign of
(that is,
)
Zero (that is,
)
sign of
0
Zero (that is,
)
denormalized
sign of number
0
Any non-zero field
w
f
b
0
s
e
f 2
w
e
1 e
11...11
=
f
10...00
= ± 2
w
e
1 e
11...11
=
f
00...00
=
0
±
0
f
00...00
=
0 0 (
)
+
0 =
0 0
+
0
=
(
)
+
= + Floating-Point Operator v4.0
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DS335 April 25, 2008
Product Specification
The Xilinx core supports formats with fraction and exponent wordlengths outside of these standard
wordlengths.
Denormalized Numbers
The exponent limits the size of numbers that may be represented. It is possible to extend the range for
small numbers using the minimum exponent value (0) and allowing the fraction to become denormal-
ized. That is, the hidden bit
becomes zero such that
. Now the value is given
by:
These denormalized numbers are extremely small. For example, with single precision the value is
bounded
. As such, in most practical calculation they do not contribute to the end result.
Furthermore, as the denormalized value becomes smaller, it is represented with fewer bits and the rel-
ative rounding error introduced by each operation is increased.
The Xilinx Floating-point core does not support denormalized numbers. In FPGAs, the dynamic range
can be increased using fewer resources by increasing the size of the exponent (and a 1-bit increase for
single precision increases the range by
). If necessary, the overall wordlength of the format can be
maintained by an associated decrease in the wordlength of the fraction.
To provide robustness, the core treats denormalized operands as zero with a sign taken from the denor-
malized number. Results that would have been denormalized are set to an appropriately signed zero.
The support for denormalized numbers cannot be switched off on some processors. Therefore, there
may be very small differences between values generated by the Floating-Point core and a program run-
ning on a conventional processor when numbers are very small. If such differences must be avoided,
the arithmetic model on the conventional processor should include a simple check for denormalized
numbers. This check should set the output of an operation to zero when denormalized numbers are
detected to correctly reflect what happens in the FPGA implementation.
Rounding Modes
Currently, only the default rounding mode, Round to Nearest, as defined by the IEEE-754 Standard, is
supported.
Signalling and Quiet NaNs
The IEEE-754 Standard requires provision of Signalling and Quiet NaNs. However, the Xilinx Floating-
Point core treats all NaNs as Quiet NaNs. When any NaN is supplied as one of the operands to the core,
the result is a Quiet NaN, and an invalid operation exception will not be raised (as would be the case for
signaling NaNs). The exception to this rule is floating-point to fixed-point conversion. For detailed
information, see the behavior of
"INVALID_OP."
Fixed-Point Number Representation
For the purposes of fixed-point to floating-point conversion, a fixed-point representation is adopted
that is consistent with the signed integer type used by Xilinx System Generator for DSP. Fixed-point
values are represented using a 2s complement number that is weighted by a fixed power of 2. The
binary representation of a fixed-point number contains three fields as shown in
Figure 3
(although it is
still simply a weighted 2s complement number).
b
0
b
0
.
b
1
b
2 b
p
1 1
<
v
1 (
)
s
2
2
w
e
1 2
0.b
1
b
2 b
w
f
1 =
v
2
126 <
2
256 DS335 April 25, 2008
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5
Product Specification
Floating-Point Operator v4.0
In
Figure 3
, the bit positi