essing Faults
missing contact windows
parasitic transistors
oxide breakdown
Material Defects
bulk defects (cracks, crystal imperfections)
surface impurities (ion migration)
Time-Dependent Failures
dielectric breakdown
electromigration
Packaging Failures
contact degradation
seal leaks Fault model.3
Faults, Errors and Failures
Fault: A physical defect within a circuit or a system
May or may not cause a system failure
Error: Manifestation of a fault that results in incorrect
circuit (system) outputs or states
Caused by faults
Failure: Deviation of a circuit or system from its
specified behavior
Fails to do what it should do
Caused by an error
Fault ---> Error ---> Failure Fault model.4
Why Model Faults ? Fault model identifies target faults Model faults most likely to occur Fault model limits the scope of test
generation Create tests only for the modeled faults Fault model makes effectiveness measurable
by experiments Fault coverage can be computed for specific test patterns
to reflect its effectiveness Fault model makes analysis possible Associate specific defects with specific test patterns Fault model.5
Fault Models
Stuck-At Faults
Bridging Faults
Transistor Stuck-On/Open Faults
Functional Faults
Memory Faults
PLA Faults
Delay Faults
State Transition Faults Fault model.6
Single Stuck-At Faults
0
1
1
1
0
1/0
1/ 0
stuck-at-0
Fault-free Response
Test Vector
Faulty Response
Assumptions:
Only one line is faulty.
Faulty line permanently set to 0 or 1.
Fault can be at an input or output of
a gate. Fault model.7
Multiple Stuck-At Faults Several stuck-at faults occur at the same time Important in high density circuits For a circuit with k lines there are
2k
single stuck-at faults there are
3
k
-1
multiple stuck-at faults Fault model.8
Why Single Stuck-At Fault Model?
Complexity is greatly reduced.
Many different physical defects may be modeled by the same logical
single stuck-at fault.
Single stuck-at fault is technology independent.
Can be applied to TTL, ECL, CMOS, etc.
Single stuck-at fault is design style independent.
Gate Arrays, Standard Cell, Custom VLSI
Even when single stuck-at fault does not accurately
model some physical defects, the tests derived for logic
faults are still valid for most defects.
Single stuck-at tests cover a large percentage of
multiple stuck-at faults. Fault model.9
Bridging Faults
A
B
f
g
A
B
f
g
A
B
f
g
A
B
f
g Two or more normally distinct points (lines)
are shorted together Logic effect depends on technology Wired-AND for TTL Wired-OR for ECL CMOS ? Fault model.10
CMOS Transistor Stuck-ON
0
stuck-on
?
IDDQ
Transistor stuck-on may cause
ambiguous logic level.
When input is low, both P and N
transistors are conducting causing
increased quiescent current, called
IDDQ fault.
depends on the relative impedances
of the pull-up & pull-down networks Fault model.11
CMOS Transistor Stuck-OPEN
0
stuck-open
?
= previous state
Transistor stuck-open may cause
output floating. Fault model.12
CMOS Transistor Stuck-OPEN (Cont.)
10
stuck-open
01/00
Initialization
vector
memory
behaviour
Can turn the circuit into a sequential one
Stuck-open faults require two-vector tests Fault model.13
Functional Faults
Fault effects modeled at a higher level
than logic for function modules, such as
Decoders
Multiplexers
Adders
Counters
RAMs
ROMs Fault model.14
Functional Faults of Decoder
f(L
i
/L
j
): Instead of line L
i
, Line L
j
is selected
f(L
i
/L
i
+L
j
): In addition to L
i
, L
j
is selected
f(L
i
/0): None of the lines are selected
2-bit
Decoder
A
B
AB
AB
AB
AB Fault model.15
Memory Faults Parametric Faults Output Levels Power Consumption Noise Margin Data Retention Time Functional Faults Stuck Faults in Address Register, Data Register,
and Address Decoder Cell Stuck Faults Adjacent Cell Coupling Faults Pattern-Sensitive Faults Fault model.16
Memory Faults (Cont.) Pattern-sensitive faults: the presence of a
faulty signal depends on the signal values
of the nearby points Most common in DRAMs Adjacent cell coupling faults Pattern sensitivity between a pair of cells
0 0 0
0 d b
0 a 0
a=b=0 d=0
a=b=1 d=1 Fault model.17
PLA Faults
Stuck Faults
Crosspoint Faults
- Extra/Missing Transistors
Bridging Faults
Break Faults Fault model.18
Missing Crosspoint Faults in PLA
A
B
C
f1 f2
A
B
C
f1
f2
Growth
Disappearance
s-a-1
s-a-0
Missing crosspoint in AND-array
- Growth fault
Missing crosspoint in OR-array
- Disappearance fault
Equivalent stuck fault representation Fault model.19
Extra Crosspoint Faults in PLA
Extra crosspoint in AND-array
- Shrinkage or disappearance fault
Extra crosspoint in OR-array
- Appearance fault
Equivalent stuck fault representation
A
B
C
f1 f2
A
B
C
f1
f2
Disapp.
"1"
Shrinkage
"0"
Appearance Fault model.20
Gate-Delay-Fault Slow to rise, slow to fall x is slow to rise when channel resistance R1 is
abnormally high
VDD
VDD
C L
X
X
L ---> H
R1 Fault model.21
Gate-Delay-Fault

Disadvantage:
Delay faults resulting from the sum
of several small incremental delay
defects may not be detected.
slow Fault model.22
Path-Delay-Fault
Propagation delay of the path exceeds
the clock interval.
The number of paths grows exponentially
with the number of gates. Fault model.23
State Transition Graph
Each state transition is associated with a 4-tuple:
(source state, input, output, destination state)
S2
S3
S1
I2/O2
I1/O1 Fault model.24
Single State Transition Fault Model
S2
S3
S1
I/O
I/O
A fault causes a single state transition
to a wrong destination state. Fault model.25
Fault Detection A test (vector) t detects a fault f iff t detects f <=> Example
x
X1
X2
X3
Z
1
Z
2
s-a-1
Z
1=X1X2
Z
2=X2X3
Z
1<i>f =X1
Z
2<i>f =X2X3
z t
( )

z
f
t
( )
=
1
The test 001 detects f because
z
1
(001)=0 while
z
1<i>f
(001)=1





( )

( ) Fault model.26
Sensitization

z
(1011)=0
z
f
(1011)=1
1011 detects the fault f (G
2
stuck-at 1)
v/v
f
: v = signal value in the fault free circuit
v
f
= signal value in the faulty circuit
X1
X2
X3
X4
G1
G2
G3
G4
1
0
1
1
1
s-a-1
0/1
1
0/1
0/1
z Fault model.27
Sensitization A test t that detects a fault f Activates f (or generate a fault effect) by creating
different v and v
f
values at the site of the fault Propagates the error to a primary output w by making all
the lines along at least one path between the fault site
and w have different v and v
f
values A line whose value in the test changes in the
presence of the fault f is said to be sensitized
to the fault f by the test A path composed of sensitized lines is called
a sensitized path Fault model.28
Detectability A fault f is said to be detectable if there
exists a test t that detects f ; otherwise,
f is an undetectable fault For an undetectable fault f No test can simultaneously activate f and create a
sensitized path to a primary output
z
f
x
( )
=
z x
( ) Fault model.29
Undetectable Fault G
1
output stuck-at-0 fault is undetectable Undetectable faults do not change the function of the
circuit The related circuit can be deleted to simplify the circuit
x
s-a-0
a
b
c
z
G1
1/0
1
1
0
0
0
1
??? Fault model.30
Test Set Complete detection test set: A set of tests
that detect any detectable faults in a class
of faults The quality of a test set is measured by fault
coverage Fault coverage: Fraction of faults that are
detected by a test set The fault coverage can be determined by fault
simulation >95% is typically required for single stuck-at fault model >99.9% in IBM Fault model.31
Fault Equivalence A test t distinguishes between faults

and if Two faults, & are said to be equivalent
in a circuit , iff the function under is equal
to the function under for any input
combination (sequence) of the circuit. for all
t No test can distinguish between

and
Any test which detects one of them detects all of them t
(
t
(
z
)
z
)
z t
( )
=
z t
( ) Fault model.32
Fault Equivalence AND gate: all s-a-0 faults are equivalent OR gate: all s-a-1 faults are equivalent NAND gate: all the input s-a-0 faults and the output
s-a-1 faults are equivalent NOR gate: all input s-a-1 faults and the output
s-a-0 faults are equivalent Inverter: input s-a-1 and output s-a-0 are equivalent
input s-a-0 and output s-a-1 are equivalent Fault model.33
Equivalence Fault Collapsing n+2 instead of 2n+2 faults need to be
considered for an n</i>-input gate.
s-a-1
s-a-1
s-a-1
s-a-1
s-a-1
s-a-1
s-a-1
s-a-1
s-a-0
s-a-0
s-a-0
s-a-0
s-a-0
s-a-0
s-a-0
s-a-0