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Advanced Engineering of PVD and ALD based Barriers for Sub-micron
Advanced Engineering of PVD and ALD based Barriers for Sub-micron
Device Generations in Dual Damascene Copper Interconnects

Prabu Gopalraja, Suraj Rengarajan, John Forster, Xianmin Tang, Rahul Jauhari, Umesh Kelkar,
Anthony Chan, Marc Schweitzer, Keith Miller, Ajay Bhatnagar, Nirmalya Maity, Jim Van Gogh,
Suketu Parikh and Hua Chung

Applied Materials Inc., 3050 Bowers Ave., Santa Clara, CA 95054

1. Introduction
The requirement of minimal bottom coverage and thick sidewall coverage for PVD-based
films for low via resistance and improved stress migration is not easy to achieve with traditional
deposition methods. Modern I-PVD techniques
1
give high bottom coverage, due to the ionized
component of the deposition flux. Sidewall coverage tends to be low, which is mainly due to off-
normal deposition flux and a less than unity sticking coefficient.
Early research into ionized PVD deposition showed that it is possible to re-sputter
material deposited onto the wafer if sufficient ion bombardment is present
2
. Inside a trench or via,
the re-sputtering of the material from the feature bottom would lead to a redistribution of the
material, often resulting in a thinner bottom coverage and a thicker sidewall coverage. If high bias
power is applied to the substrate during deposition, thicker sidewall coverage near the via bottom
will be observed
2
.
The use of re-sputtering to reduce barrier thickness at the bottom of a dual damascene
via bottom has been shown to reduce via resistance (Rc), improve Rc distribution and increase
resistance to electromigration effects
3,4,5,6,7
. This paper describes experiments performed on a
novel ionized PVD source that shows how such process optimization leads to lower contact
resistance and better EM and SM performance.
As Cu interconnect line widths are reduced below 90nm, the requirement arises for a
highly conformal barrier layer that provides an effective diffusion barrier between Cu and the low-
k material, with very low barrier thicknesses (~1 to 2nm). This ensures that the fraction of higher
resistivity barrier material is kept to a minimum within the Cu interconnect, to ensure that the
overall line resistivity stays low, while line widths are reduced
8
. We have found that ultra-thin TaN
films, deposited using ALD techniques, can provide 100% step coverage. This paper also looks
at some of the unique results observed with these thin films.
2. Experimental
The source used in this work consists of a magnetron sputter source combined with an
inductively coupled plasma source. It differs from traditional inductively coupled ionized PVD
sources in that the magnet has been designed to yield ionization of the sputtered Ta on the order
of 20-50%, without application of any power to the induction coil
9
. Deposition typically occurs with
high target power and at low pressure. The inductively coupled plasma is used solely during the
re-sputtering, or etch, process. All the touted advantages of a high density plasma source come
into play, such as allowing for independent control of the ion energy and ion density. The
induction coil consists of the same material as the sputter target, and it is placed inside the
process chamber. It is possible to sputter material both from the coil and the target during the
etch process. This allows etching of the corners to be minimized without a large reduction of the
etch rate at the via bottom. The coil is a single loop and is powered with RF frequency. A DC
power source is also attached to the coil, and the DC power level is used to control the rate of coil
sputtering. A schematic layout of the source is shown in Figure 1. The ALD TaN films were
deposited in the Åltra ALD chamber, in the Applied Materials Endura
®
iCuB/S system.
3. Results
3a. Deposition
The step coverage that is achieved during the deposition process depends on the
ionization fraction of the sputtered metal. In this source this fraction depends on the DC target
power and the pressure. Typically, higher deposition rates and ionization are achieved with
increasing DC bias resulting in increased bottom coverage (Figure 2). The bottom coverage
increases with increasing bias, due to the resulting increasing directionality of metal ions. If the
bias were increased beyond ~500W, the energy of the metal ions would be high enough to cause
net sputtering at the via bottom, leading to a decrease in bottom coverage.
3b. Re-sputtering/Etching
The DC target power, the pressure, the RF coil power, the substrate bias, and the DC
power applied to the coil influence the re-sputter process. The substrate bias has the largest
effect on etch rate. The etch rate is the difference between the rate of sputtering at the wafer
surface, and the arrival rate of Ta at the wafer surface. The etch rate increases with substrate
bias (Figure 3). Increasing the bias power increases the ion bombardment energy, which
increases the sputter rate of Ta at the wafer surface. The etch rate decreases with increasing DC
power to the target and increasing DC power to the coil. Increasing DC power to the target and
increasing DC power to the coil both increase the sputter rate of the target and coil, leading to an
increase in the arrival rate of Ta at the wafer surface.
3c. Combined Deposition and Etch Process
Conceptually, there are several types of deposition and re-sputter processes that are
possible. For example, it is possible to reactively deposit TaN, then re-sputter, then deposit Ta,
and then re-sputter again. Alternatively, it is possible to deposit a bi-layer of TaN and Ta, and
then perform a single re-sputter process step. Other modifications involve punch through during
the re-sputter steps followed by a thin Ta flash layer. Whichever process is optimized, the final
barrier film must exhibit good stress migration results, low via resistance and good
electromigration characteristics. Figure 4a shows a via bottom with an as-deposited film and
Figure 4b shows the via after re-sputtering showing complete removal of the barrier film from the
via bottom. Figure 4c shows a typical dual damascene structure with optimal PVD step coverage
obtained with the deposition and etch process. The source has been optimized to provide
uniform deposition and etch control capability at the center and edge of the wafer for tight Rc
distribution.
3d. ALD TaN Process
ALD relies on self-limiting chemisorption of a reactant molecule (precursor) on the
substrate surface. The self-limiting behavior implies that the deposition rate per cycle is
determined mainly by the saturation time and is independent of the reactant exposure time after
saturation is obtained. Surface saturation characteristically occurs very fast, with sub-second
timing.

For example, in the ALD TaN process, the (tantalum) precursor saturates within 0.5
seconds for an average deposition rate of a (~0.5Å) per cycle.
Since ALD relies on self-limiting surface chemisorption, ALD reactions in general can
occur at a lower temperature than conventional thermal CVD, enabling integration with low
thermal budget process flows. The ALD TaN films for Cu barrier application are deposited at a
temperature of 300
o
C, and are thus compatible with Cu low-k integration. The ultra thin TaN
films, deposited using ALD techniques, can provide 100% step coverage with <15Å thickness and
non-uniformity of <3%, 1 on 300mm wafers (Figure 5).
4. Electrical Results on Wafers
Figure 6 compares the via resistance between a wafer processed with a combined
deposition and etch process to a wafer processed with a pure deposition process. The plot shows
the cumulative distribution of via resistance. The resistance (x-axis of the plot) is the measured resistance of 112,000 series connected vias. The combined deposition and etch process wafer
had a significantly lower via resistance compared to the deposition only process wafer. Also, the
via resistance distribution for this process was observed to be much tighter than the deposition
only process
6,7
.
Figure 7 shows the time it takes for the electrical test structures to exhibit a 5% change in
via resistance while applying a current density of 1MA/cm
2
, with the wafer held at a temperature
of 300
o
C. This procedure tests the ability of the test structures to resist EM effects. The wafers
processed with the deposition only process showed a significant number of early failures (fail time
< 10hr), whereas the wafer processed with the combined deposition and etch process exhibited
fail times of greater than 100hr.
Figure 8 compares the stress migration results of the film after 175
o
C at 168 hours, post
anneal and post CMP. The Rc distribution appears unchanged after these tests, showing the
effectiveness of the re-sputtered barrier film as a diffusion barrier.
To verify the integration of the ALD TaN barrier in Cu metallization, electrical testing