r>support for the R300EX, consistent with Intels commitment to support of the
Intel386 EX.
The R300EX is designed specifically for use with the Intel386 EX. It
provides the support required by the Intel386 EX and its peripheral devices.
This includes DRAM, Flash or EPROM control, Reset synchronization,
Ready generation, data bus transceiver control, and support for the
Synchronous Expansion Bus.
The DRAM controller includes address multiplexers, page hit logic for
address pipelining, RAS and CAS generation, and refresh control.
The R300EX provides control signals for Flash memory, real time clock
chips, IDE interface, and keyboard/mouse controller chips. It also generates
a clock synchronized RESET signal for the Intel386 EX, and the READY#
signal for non Local Bus Access cycles. Signals are generated for the
Synchronous Expansion Bus (SEB), which is a subset of the ISA bus.
Additionally, a data buffer control signal is provided to prevent data bus
contention that could result from direct use of the Intel386 EX RD# signal as
the output enable for external devices.
R300EX Feature Summary

Supports Intel386 EX
A-Step, B-Step, and full
33MHz C-Step processors

Pipelined, zero wait state,
fast page mode DRAM
controller for fast system
response

Complete support for 1, 2,
4, 8, and 16MB DRAM
memory systems

Integrated DRAM address
multiplexers

CAS before RAS refresh

Support for Flash ROM,
real time clock, IDE, and
keyboard controllers

100 pin PQFP

Integrated dynamic bus
sizing and READY#
generation minimizes
external logic

Reset - CLK
synchronization for
Intel386 EX

Implements an ISA-subset,
Synchronous Expansion
Bus (SEB)

Shutdown cycle - NMI
generation circuit for PC-
like shutdown cycle
handling

Fully tri-stateable with
NAND-tree output for
ATE (bed of nails) testing RadiSys R300EX Memory/Bus Controller
November, 95
Page 2 of 37
Technical Overview:
Intel386 EX Processor Support
The R300EX supports the 5V Intel386 EX C-step device
up through 33MHz. It also supports the 5V B-step device
up through 25MHz. The 5V A-step is supported up
through 25MHz with NA# not connected.
DRAM Control
The fast page mode DRAM controller provides complete
support for 1, 2, 4, 8, and 16MB memory systems. The
integrated page hit register enables the system to run zero
wait states, rather than two, on a pipelined, same page
access.
Systems using a 33MHz C-step version of the Intel386 EX
processor need 60nS or better fast page mode DRAM. To
run with a 25MHz B-step Intel386 EX, systems can use
70nS or better DRAMs.
The DRAM controller integrates the address multiplexers
and CAS before RAS refresh circuitry to simplify system
design.
Flash Control
Control logic provides support for Flash memory. The
chip generates the proper write enable and chip selects to
support programming of Boot Block Flash Memory
systems. It also supports accessing the same Flash device
at the top of both the 64M and the 1M address space.
Synchronous Expansion Bus
The Synchronous Expansion Bus (SEB)

implements a
functional subset of the ISA bus. It is intended to allow a
selected set of peripherals to be used without implementing
an entire ISA bus. The SEB is asynchronous from the
peripherals point of view, but is generated synchronously
to the Intel386 EX processor. The SEB includes:

Intel386 EX processor address line A25-A1, BHE#
and BLE#

Buffered data bus D15-D0

Command strobes, IOR#, IOW#, MEMR#, MEMW#,
BALE

Control input IOCHRDY, MEMCS16#, IOCS16#
The R300EX generates or recognizes:

IOR#

IOCS16#

IOW#

MEMCS16#

MEMR#

IOCHRDY

MEMW#

BALE#
SMEMR# and SMEMW# are not generated by the
R300EX, but they can be easily generated from MEMR#
and MEMW#. 0WS# is not supported.
Data Bus Sizing
The R300EX generates the BS8# signal used in
conjunction with the dynamic bus sizing capability of the
Intel386 EX processor. This capability provides the 16 bit
to 8 bit conversion cycles that are necessary when an 8 bit
device is accessed with a word bus cycle.
Wait States and Ready Generation
The R300EX generates READY# to terminate any bus
cycle that is not an Intel386 EX local bus access. Those
cycles that do not have LBA# active include
Halt/Shutdown cycles, SEB and DRAM accesses, and
Flash accesses below 1MB.
Wait states are generated as part of the READY# logic.
Two wait states are inserted into Flash accesses. DRAM
accesses vary in length from 0 to 2 wait states depending
on the type of access (page hit or miss for example).
Halt/shutdown and 16-bit SEB cycles are 8 CPU wait
states, while 8-bit SEB cycles are 15 CPU wait states.
This
is
the equivalent of 2 and 4 ISA wait states respectively.
SEB accesses can be extended using IOCHRDY.
The R300EX drives READY# when LBA# is not active. It
is forced high for the cycle immediately after it is sampled
low by the CPU. Any time LBA# is active, the READY#
output will be tri-stated.
Preventing Data Bus Contention
An integrated bus tracker state machine follows the CPU bus
activity. The bus tracker generates a signal used to disable
the data bus transceivers between the CPU and peripheral
devices. This buffer eliminates the possibility of data bus
contention when the CPU transitions from a read cycle to a
write cycle. This signal disables the transceivers for all T1,
T1P, and Ti cycles following T2 and T2P cycles.
CPU Shutdown Recognition
CPU Shutdown cycles are recognized by the R300EX, and
it will assert the NMI signal in response. The NMI signal is
released when the UCS# signal is detected. This allows the
NMI service routine to handle shutdown cycles in a
manner similar to PCs.
Real Time Clock Control
The R300EX generates the necessary AS and DS control
signals to interface real time clock chips like the
MC1468C18A to the Intel386 EX.
IDE Interface Control
Data bus control signals for an IDE interface are generated
by the R300EX. The access time and bus size for IDE
transfers are determined through the use of IOCS16#.
These cycles run with the standard 8 or 15 wait states of
the Synchronous Expansion Bus. RadiSys R300EX Memory/Bus Controller
November, 95
Page 3 of 37
Keyboard/Mouse Controller Access
The R300EX generates ISA-like I/O read and write strobes
for the keyboard/mouse controller which it expects to find
on the local address and data buses. By configuring the
Intel386 EX CS1# for I/O addresses 60h and 64h with zero
wait states and external READY, these accesses will be run
as 15 wait state, 8-bit SEB I/O cycles with the R300EX
returning READY#.
CLK-Reset Synchronization
The RESET signal is generated from the CLK2 and
PWRGD input signals. The RESET signal output to the
Intel386 EX is synchronized with the rising edge of CLK2,
and is also used internally to keep track of clock phase as
part of the bus tracker state machine.
R300EX Package and Test Features
The R300EX comes in a 100 pin PQFP package, with an
enhanced capability that eases system testing. All outputs
are fully tri-stateable for use in conjunction with an internal
NAND-Tree that links all of the pins back to a single
output. Using a bed-of-nails ATE tester, and tri-stating the
device, it is possible to verify that all of the pins on the
device are connected to the circuit board.
The RadiSys Advantage
The RadiSys R300EX is a low cost component which
greatly simplifies Intel386 EX systems that are designed to
run PC oriented applications. As a company, RadiSys is
committed to long term support for our products. Unlike
designing with the short lived parts from the PC chipset
commodity market, this RadiSys commitment makes
designing with the R300EX a safe bet.
Figure 1: Example
System using R300EX RadiSys R300EX Memory/Bus Controller
November, 95
Page 4 of 37
Table 1: RadiSys R300EX Pin Definition
Pin
Function
Pin
Function
Pin
Function
Pin
Function
1
A9
26
A4
51
MA7
76
Vss
2
A8
27
CS3#
52
MA6
77
MA0
3
A11
28
Vss
53
Vdd
78
BALE
4
A21
29
A3
54
WE#
79
TEST
5
Vdd
30
A2
55
MA5
80
NC
6
CS1#
31
MA10
56
M/IO#
81
RTC_AS
7
A7
32
KBDCS#
57
MA4
82
NC
8
IOCHRDY
33
A14
58
BLE#
83
MEMW#
9
A6
34
A18
59
MEMCS16#
84
Vdd
10
FLSHA18
35
CASBH#
60
NAND_OUT
85
A22
11
IDE_ENL#
36
Vdd
61
Vss
86
A13
12
IDE_ENH#
37
A20
62
A10
87
IOW#
13
Vss
38
CASAH#
63
FLSHWE#
88
Vss
14
DATA_DE
39
D/C#
64
MA3
89
CLK2
15
FLSHCS#
40
Vss
65
MEMR#
90
LBA#
16
CS2#
41
Vdd
66
A23
91
Vss
17
A1
42
PWRGD
67
BS8#
92
A19
18
RAS#
43
RDY#
68
Vdd
93
Vdd
19
ONE_4MEG
44
MA9
69
RESET
94
CS5#
20
Vdd
45
Vss
70
NMI
95
CS4#
21
CASAL#
46
IOCS16#
71
RTC_DS
96
A16
22
A12
47
UCS#
72
MA2
97
Vss
23
NA#
48
MA8
73
A17
98
W/R#
24
A5
49
BHE#
74
MA1
99
ADS#
25
CASBL#
50
CS6#
75
I/OR#
100
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A9
A8
A11
A21
Vdd
CS1#
A7
IOCHRDY
A6
FLSHA18
IDE_ENL#
IDE_ENH#
Vss
DATA_DE
FLSHCS#
CS2#
A1
RAS#
ONE_4MEG
Vdd
CASAL#
A12
NA#
A5
CASBL#
A4
CS3#
Vss
A3
A2
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
TEST
BALE
MA0
Vss
IOR#
MA1
A17
MA2
RTC_DS
NMI
RESET
Vdd
BS8#
A23
MEMR#
MA3
FLSHWE#
A10
Vss
NAND_OUT
MEMCS16#
BLE#
MA4
M/IO#
MA5
WE#
Vdd
MA6
MA7
MA10
KBDCS#
A14 A18
CASBH#
Vdd A20
CASAH#
D/C# Vss Vdd
PWRGD RDY#
MA9 Vss
IOCS16#
UCS# MA8 BHE# CS
6#
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
RTC_AS
NC
MEMW#
Vd
d
A2
2
A1
3
IOW#
VSS
CLK2
LBA#
Vss
A1
9
Vd
d
CS
5#
CS
4#
A1
6
Vss
W/R#
ADS#
A1
5
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
RadiSys
R300EX
Figure 2: RadiSys R300EX 100 Pin PQFP Pin Assignment RadiSys