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Industrial Controller System -
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Page 1 of 2
April 2006, ExApp32_IC_Apps.doc
Issue No. 32
PEX 8311 Key Features
Generic Local Bus to PCI Express
Bridge
Root Complex and EndPoint
Modes of Operation
Local Bus Modes:
- 32-bit address & 32-bit data (C-Mode)
- Multiplexed 32-bit address/data (J-Mode)
Local Clock rates up to 66MHz
Zero wait state bursts to 264MB/s
Integrated SERDES
2 DMA channels
21x21 mm
2
, 337 pin PBGA
Typical Power: under 1.0 Watt
Other Features
Integrated PCIe Interface
Compliant to PCIe r1.0a
x1 Link, 2.5 Gbps / direction
Auto Polarity Reversal
Link CRC Support
Link / Device Power Management
Flow Control Buffering
PCIe Transaction Queues for Eight
outstanding TLPs
Direct Master Data Transfers
Direct Slave Data Transfers
Configuration Through Host or
Optional EEPROM
On-the-fly Endian Conversion
8 Mailbox & 2 Doorbell Registers
Four GPIO, 1 GPI, 1 GPO
I2O Messaging Unit
Application:
Industrial Controller System
PLX Product:
PEX 8311 Local Bus to PCIe Bridge
Key Benefit:
Full Connectivity to PCIe components
New Industrial Control Systems Migrating
to PCI Express Designs
Industrial control systems have traditionally been extremely limited in
their scalability and performance. A typical design would monitor
production lines and provide periodic feedback when a parameter falls
out of specification. An alarm would be triggered and the line would
then be shut down until a corrective action is taken. With economic
competition and the need for advanced operations reaching a fever
pitch, this method is becoming obsolete. New designs demand real-
time feedback and correction without halting production. Factories are
routinely providing instantaneous feedback from a variety of sources
to a central host for analysis. When an error is detected, only the
specific operations are throttled back or stopped. To implement such
systems, an intelligent industrial controller analyzes and feeds
operations data to a central host through the network. Performance,
scalability to industrial strength factories, traffic prioritization, and
multiple channels are a must. PCIe interconnect technology fits the
need.
PEX 8311 Supports Full Protocol Translations
The PEX 8311 is a bridge from a low overhead parallel generic local
bus (used by various processors, DSPs, memory, and FPGA designs)
to a PCIe port. In this conversion, the bridge completely translates data
from the local bus into PCIe packets with full packet header
generation. Address spaces from the local bus and PCIe domain are
fully translated. Out-of-band signals on the local bus are translated into
message signaling interrupt (MSI) packets and vice versa. The bridge
supports all transaction types. Full on-chip buffers provide flow
control and the link layer CRC ensures data integrity. -
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Page 2 of 2
April 2006, ExApp32_IC_Apps.doc
Issue No. 32
Multiple DMA Channels are Key
Figure 2 shows the PEX 8311 used in an industrial
controller. Here multiple sources of analog feedback
including infrared, heat, and video images from a
production line are converted to digital format and
passed to an FPGA for local processing and then
through the bridge. The bridge converts traffic to
PCIe and passes it through an aggregation switch,
such as PLXs PEX 8532, and then passes it to the
host controller for analysis and corrective action.
FPGA devices routinely use a local bus type
interface and connect with no glue logic to the PEX
8311 bridge. As there are multiple streams of data,
several bridges are used in the design. A local CPU
is used to manage this traffic flow. Memory or other
components may also be present on this local bus.
Figure 2
In order to more efficiently transfer data through this
system, it is preferable to have multiple DMA
channels present. The DMA controllers take a set of
instructions from the local CPU or Host and control
the transfer of data through the bridge negating the
need for host intervention. With two DMA channels
present, it simplifies the design as one set of
descriptors can be loaded into one DMA channel
while the second channel transfers data. In the case
of a smaller packet size, throughput can be increased
by 30%. A second use of multiple DMA channels is
to allow simultaneous bi-directional traffic, in this
case, control data from the host back to the source.
No need exists to complete one transfer before
starting the second.
Additional PEX 8311 Capabilities
Such Industrial Controller Systems often require
large numbers of devices present on the local bus
and have high bandwidth needs. Local bus devices
need to communicate with each other and not just
through the bridge. The PEX 8311 has the capability
to handle up to five simultaneous loads present on
the local bus with up to 32-bit and 66MHz operation.
In addition, the PEX 8311 includes Direct Master
and Direct Slave operation simultaneously with
DMA. As these modes have higher priority than
DMA, they can be used to provide control data or
other throughput that cannot be blocked by DMA
transfers. To enhance throughput even more, the
Read Ahead mode allows data to be obtained and
stored in internal FIFOs before it is sent through the
bridge.
Design Tools & Documentation:
On PLX Public ToolBox:
http://www.plxtech.com/products/pci_express/P
EX8311/default.asp
Data Book, BSDL, IBIS and HSPICE Models,
RDK, OrCAD Symbols and Gerber files.
Contact Information
PLX Technology, Inc.
870 Maude Ave.
Sunnyvale, CA 94085 USA
Tel: 1-800-759-3735
Tel: 1-408-774-9060
Fax: 1-408-774-2169
Applications Support: Local FAE
Product Marketing:
Krishna Mallampati
kmallampati@plxtech.com
Web Site: www.plxtech.com
8311-SIL-EA-1.0
© 2006 PLX Technology, Inc. All rights reserved. Expresslane, PLX and the PLX
logo are registered trademarks of PLX Technology, Inc. The ExpressLane logo is
a trademark of PLX Technology, Inc., which may be registered in some jurisdiction.
All other product names that appear in this material are for identification purposes
only and are acknowledged to be trademarks or registered trademarks of their
respective companies.
Information supplied by PLX is believed to be accurate and
reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may
appear in this material. PLX Technology, Inc. reserves the right, without notice, to
make changes in product design or specification.
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
CPU
Memory
PEX 8311
PEX 8311
PEX 8311
PEX 8311
PEX 8311
PEX 8311
PEX 8311
PEX 8311
PEX 8311
PEX 8311
PEX 8311
PEX 8311
PEX 8532
PEX 8532
PEX 8532
Host
250MB/s
250MB/s
250MB/s
250MB/s