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A Note About VRAMs
August 1995 Hewlett Packard Journal
11
A Note About VRAMs
Video RAMs, or VRAMs, are a variety of two-port dynamic RAM. They are de-
signed to work well in graphics and video applications. The main port allows ran-
dom access to any cell of the RAM. The other port consists of shift registers that
are controlled by an independent clock. In the HP S1010A, the random port runs in
the video input clock domain, and the serial port runs in the flat panel clock do-
main.
A data transfer operation loads the shift registers with data from the RAM array.
The shift registers can be treated as two semi-independent halves, so that one half
can be loaded without interfering with the data being shifted out of the other half.
This provides more flexibility, since a data transfer operation (called a split data
transfer in this case) can happen at any time while the other half is active, and
transfers can be arranged so that there will be no interruption in the data flow out
of the shift registers. The VRAM provides a signal called qsf to indicate which half
of the shift register is active. When the data in the active half of the shift register is
exhausted, qsf toggles, and the other half becomes active. This signals the HP
S1010As control logic that its time to get ready for another split data transfer.
get an even ratio of eight flat panel frames for every nine
input video frames.
After transfer of the last active line of video to the flat panel
display, the state machine goes to the Extra Lines state
where it will stay for eight horizontal flat panel lines (the
eight line vertical front porch for the current frame). The
state machine then goes to the Sync Pulse state for four lines
where it drives the flat panel vertical sync signal. It then
goes back to the Nonsync state where it begins a new active
line. This cycle repeats for seven flat panel display frames.
On the eighth frame, the transition out of the Nonsync state
goes to the Holdoff state. The state machine stays in Holdoff
until
VSYNC
arrives from the input side. This is the signal to
start the cycle again with another flat panel vertical sync. At
this point, the input side and the flat panel display side of
the frame buffer are synchronized.
Remember that one frame gets discarded. This frame is the
first incoming frame after the synchronization event. Since
the video input side has a 64 line vertical back porch, and
the flat panel display side has none, the flat panel side will
require a new frame of data immediately following the syn
chronization event, but the input side will not even start to
write any valid data into the frame buffer until 64 horizontal
lines later. In addition, since the input side is faster, it will
catch up to the flat panel side sometime during this first
frame causing a video tear. By not writing this first frame of
data into the frame buffer, we can avoid the video tear. This
is illustrated in Fig. 9. The numbers in the figure indicate
frames. Note that frame 0, which is the first frame in a se
quence of nine frames, is not written into the frame buffer.
The write enable signal controls writing a frame into the
frame buffer. When low, the frame is skipped by not writing
it into the frame buffer.
Acknowledgments
Many people made significant contributions to the design of
this product. Bob Myers and Monish Shah gave valuable
technical advice, John Metzner wrote the color centering
software, Stuart Yoshida worked on the mechanical design,
Howell Felsenthal managed the mechanical design team, and
Paul Cacciola designed the power supply. Osamu Suzuki
and Sunny Hattori were our communication channel to the
flat panel vendors. Nancy Venturato provided marketing
support, and Steve Grotheer and Tony Barton managed the
unusual manufacturing requirements. The people who
helped with field support, regulatory compliance, printed
circuit board layout, and environmental test were critical,
and unfortunately, too many to name. Last, but by no means
least, we would like to thank Steve Becker, project manager
for the electrical design team, and Mike Myshatyn, section
manager for the electrical design team, for their support
.