UM PHOSPHIDE DHBT TECHNOLOGY
By
Steven Eugene Turner
B.S. University of Maine, 2001
M.S. University of Maine, 2003
A THESIS
Submitted in Partial Fulllment of the
Requirements for the Degree of
Doctor of Philosophy
(in Electrical Engineering)
The Graduate School
The University of Maine
May, 2006
Advisory Committee:
David E. Kotecki, Associate Professor of Electrical and Computer Engineering,
Advisor
Donald M. Hummels, Castle Professor of Electrical and Computer Engineering
Richard O. Eason, Associate Professor of Electrical and Computer Engineering
Bruce E. Segee, Associate Professor Electrical and Computer Engineering
Ali Abedi, Assistant Professor Electrical and Computer Engineering LIBRARY RIGHTS STATEMENT
In presenting this thesis in partial fulllment of the requirements for an advanced
degree at The University of Maine, I agree that the Library shall make it freely available
for inspection. I further agree that permission for fair use copying of this thesis for
scholarly purposes may be granted by the Librarian. It is understood that any copying
or publication of this thesis for nancial gain shall not be allowed without my written
permission.
Signature:
Date: HIGHSPEED DIGITAL AND MIXEDSIGNAL COMPONENTS
FOR X AND K
U
BAND DIRECT DIGITAL SYNTHESIZERS IN
INDIUM PHOSPHIDE DHBT TECHNOLOGY
By Steven Eugene Turner
Thesis Advisor: Dr. David E. Kotecki
An Abstract of the Thesis Presented
in Partial Fulllment of the Requirements for the
Degree of Doctor of Philosophy
(in Electrical Engineering)
May, 2006
Recently reported double heterojunction bipolar transistor (DHBT) devices manufac-
tured in Indium Phosphide (InP) technology with f
t
and f
max
both over 300 GHz enable
advanced high-speed digital and mixed-signal circuits. In this thesis, the use of InP
DHBT devices for high-speed accumulator circuits and X and K
u
band direct digital
synthesizer (DDS) circuits are investigated. At these frequencies, new technological
challenges in the design of digital and mixed-signal circuits arise in areas including
power consumption and clock distribution. This thesis addresses the speed/power trade-
offs in high-speed accumulator designs, the design of DDS circuits, and clock distri-
bution simulation. The results of six accumulator circuits and two DDS circuits are
reported as part of this thesis. The fastest 4-bit accumulator at a 41 GHz clock rate is re-
ported, as well as the fastest DDS circuits operating at 13 GHz and 32 GHz clock rates.
The 13 GHz DDS has a worst case spurious-free dynamic range (SFDR) of 26.67 dBc
and consumes 5.42 W of power, while the 32 GHz DDS has a worst case SFDR of
21.56 dBc and consumes 9.45 W of power. In addition to the circuit designs, a method-
ology for simulating electrically long clock interconnects and a new gure of merit for
comparing DDS designs are developed. ACKNOWLEDGMENTS
This work was supported by the U. S. Army Research Laboratory and by the
Defense Advanced Research Projects Agency (DARPA) under Contract DAAD17-02-
C-0115.
For supporting this work, the author would like to thank Dr. John Zolper and
Dr. Steve Pappert at DARPA, Dr. Alfred Hung at Army Research Lab, and Mr. Frank
Stroili at BAE Systems. For technical advice and insight, the author would like to thank
Mr. Richard B. Elder, Jr., Mr. Douglas Jansen, and Mr. Jeffrey Feng at BAE Systems.
For taking part in the thesis committee, the author would like to thank Dr. Ali Abedi,
Dr. Richard O. Eason, Dr. Donald M. Hummels, and Dr. Bruce E. Segee. Finally, the
author wishes to thank and extend his gratitude to Dr. David E. Kotecki for advising this
thesis and supporting this work.
ii TABLE OF CONTENTS
ACKNOWLEDGMENTS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ii
LIST OF TABLES
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
LIST OF FIGURES
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
LIST OF ABBREVIATIONS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
Chapter
1. Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1.1. Major Design Challenges for High-Speed Digital and Mixed-
Signal HBT Circuitry
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
1.1.1.
Power Consumption Issues
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
1.1.2.
Clock Distribution Issues
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
1.2. Power/Speed Trade-Off
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
1.2.1.
Timing Path Optimization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
1.2.2.
Architecture Modications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
1.2.3.
Supply Voltage Reduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
1.3. Motivation for Project
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
1.4. Review of Previously Reported Work on Digital and Mixed-
Signal HBT Circuits
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5. Thesis Organization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2. HBT Circuit Design
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1. Vitesse VIP-2 Process
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2. Circuit Simulation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3. Clock Distribution Simulations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4. Emitter Coupled Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.1.
Voltage Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4.2.
Current Mode Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.5. Voltage Swing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.6. Bias Current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.7. Current Source Output Resistance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.8. Conclusion
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3. Design of Adders and Accumulators in InP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1. Review of Adder and Accumulator Basics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1.1.
Full Adder
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1.2.
Carry Ripple Adder
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1.3.
Carry Lookahead Adder
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
iii 3.1.4.
Pipelined Adders
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1.5.
Accumulators
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2. High-Speed 4-bit Accumulators
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.1.
Test Circuits
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2.2.
Measurements
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2.3.
Accumulator ACCV1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2.3.1.
Simulation Results
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2.3.2.
Measurement Results
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2.3.2.1.
TC6 Measurement Results
. . . . . . . . . . . . . . . . . . . . 49
3.2.3.2.2.
TC7 Measurement Results
. . . . . . . . . . . . . . . . . . . . 54
3.2.4.
Accumulator ACCV2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.2.4.1.
Simulation Results
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.2.4.2.
Measurement Results
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.2.5.
Accumulator ACCV3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.2.5.1.
Simulation Results
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .