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7 A H-Bridge for DC-Motor Applications Data Sheet TLE 6209 R
P-DSO-20-12

7 A H-Bridge for DC-Motor Applications
Data Sheet
TLE 6209 R

Data Sheet, Version 3.0
1
2001-10-15
1
Overview
1.1
Features
Delivers up to 6 A continuous and 7 A peak current
Optimized for DC motor management applications
Very low
R
DS ON
of typ. 150 m
@ 25 °C per switch
Operates at supply voltages of up to 40V
Overvoltage Protection against transients up to 45 V
Outputs fully short circuit protected
Standard SPI-Interface, daisy chain capability
Adjustable chopper current regulation of up to 7 A
Temperature monitor with prewarning, warning and shutdown
Over- and Undervoltage-Lockout
Open load detection
Detailed load failure diagnosis by SPI
Minimized power dissipation due to active free-wheeling
Low EMI due to voltage slope regulation
Very low current consumption (typ. 20
µA @ 25 °C) in stand-by (Inhibit) mode
Enhanced power P-DSO-Package

Functional Description
The TLE 6209 R is an integrated power H-Bridge with D-MOS output stages for driving
bidirectional loads such as DC-Motors. The design is based on Infineons Smart Power
Technology SPT which allows bipolar, CMOS and power D-MOS devices on the same
monolithic circuit.
Operation modes forward (cw), reverse (ccw) and brake are invoked by two control pins
PWM and DIR. Protection and a reliable diagnosis of overcurrent, openload, short-circuit
to ground, to the supply voltage or across the load are integrated. Detailed diagnostic
information is given via the 8 bit SPI status word. An integrated chopper current limitation
limits the current e.g. to reduce power dissipation during mechanical block of a DC
Type
Ordering Code
Package
TLE 6209 R
Q67007-A9488
P-DSO-20-12 TLE 6209 R
Data Sheet, Version 3.0
2
2001-10-15
motor. Several device parameters can be set by the SPI control word. A three-level
temperature monitoring with prewarning, warning and shutdown is included for
controlled operation under critical power loss conditions. The full protection and
diagnosis capability make the device suitable especially for safety relevant applications,
e.g. in automotive ECUs.
1.2
Pin Configuration
(top view)
Pin Definitions and Functions
V
S
Power Supply Voltage
V
CC
5 V Logic Supply
DRV
Input for Charge pump buffer
capacitor
GND
Ground
SDI
Serial Data Input
SDO
Serial Data Output
SCLK
Serial Clock Input
CSN
Chip-Select-Not Input
OUT
Power Output
PWM
PWM Input
DIR
Direction Input
DIS
Disable Input
INH
Inhibit
OUT 2
OUT 2
INH
GND
GND
CSN
OUT 1
SCLK
SDI
SDO
OUT 1
V
S
GND
V
S
V
CC
GND
DRV
PWM
DIR
DIS
Metal slug,
connected to GND
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
19
18
17
20
10
TLE 6209R TLE 6209 R
Data Sheet, Version 3.0
3
2001-10-15
1.2.1
Pin Definitions and Functions
Pin No. Symbol Function
1, 10,
11, 20
GND
Ground; internally connected to cooling tab (heat slug); to reduce
thermal resistance place cooling areas and thermal vias on PCB.
2,3
OUT1
Output 1; output of D-MOS half bridge 1; external connection
between pin 2 and pin 3 is necessary.
4,17
V
S
Power supply; needs a blocking capacitor as close as possible to
GND; 47
µF electrolytic in parallel to 220 nF ceramic is
recommended; external connection between pin 4 and pin 17 is
necessary.
5
SCLK
Serial clock input; clocks the shiftregister; SCLK has an internal
active pull down and requires CMOS logic levels
6
SDI
Serial data input; receives serial data from the control device;
serial data transmitted to SDI is an 8 bit control word with the Least
Significant Bit (LSB) being transferred first; the input has an active
pull down and requires CMOS logic levels; SDI will accept data on
the falling edge of SCLK-signal; see Table 1 for input data protocol.
7
SDO
Serial-Data-Output; this tri-state output transfers diagnosis data to
the control device; the output will remain tri-stated unless the device
is selected by a low on Chip-Select-Not (CSN); SDO state changes
on the rising edge of SCLK; see Table 4 for diagnosis protocol.
8
CSN
Chip-Select-Not input; CSN is an active low input; serial
communication is enabled by pulling the CSN terminal low; CSN
input should only be transitioned when SCLK is low; CSN has an
internal active pull up and requires CMOS logic levels.
9
INH
Inhibit input; has an internal pull down; device is switched in
standby condition by pulling the INH terminal low.
12
DIS
Disable input; has an internal pull up; the output stages are
switched in tristate condition by pulling the DIS terminal high.
13
DIR
Direction input; has an internal pull down; TTL/CMOS compatible
input.
14
PWM
PWM input; has an internal pull down; TTL/CMOS compatible
input.
15
V
CC
Logic supply voltage; needs a blocking capacitor as close as
possible to GND; 10
µF electrolytic in parallel to 220 nF ceramic is
recommended. TLE 6209 R
Data Sheet, Version 3.0
4
2001-10-15
1.3
Functional Block Diagram

Figure 1
Block Diagram
16
DRV
Drive; Input for external charge pump capacitor
C
DRV
18,19
OUT2
Output 2; output of D-MOS half bridge 2; external connection
between pin 2 and pin 3 is necessary.
1.2.1
Pin Definitions and Functions (contd)
Pin No. Symbol Function
Bias
Inhibit
Charge
Pump
S
P
I
UV
OV
TSD
Fault-
Detect



1
V
CC
INH
SCLK
SDO
SDI
CSN
DRV
PWM
DIR
V
S
GND
OUT 2
OUT 1
DIS
Driver
&
Gate-
Control
1,10,11,20
16
15
4,17
2,3
18,19
14
13
7
5
6
8
12
9
Direct
Input
8 Bit
Logic
and
Latch TLE 6209 R
Data Sheet, Version 3.0
5
2001-10-15
2
Circuit Description
2.1
Serial Peripheral Interface (SPI)
The SPI is used for bidirectional communication with a control unit. The 8-bit
programming word or control word (see Table 1) is read in via the SDI serial data input,
and this is synchronized with the serial clock input SCLK. The status word appears
synchronously at the SDO serial data output (see Table 4).
The transmission cycle begins when the chip is selected with the chip-select-not (CSN)
input (H to L). When the CSN input changes from L to H, the word which has been read
into the shift register becomes the control word. The SDO output switches then to tristate
status, thereby releasing the SDO bus circuit for other uses. The SPI allows to parallel
multiple SPI devices by using multiple CSN lines. Due to the full duplex shift register, the
TLE 6209 R can also be used in daisy-chain configuration.
The settings made by the SPI control word become active at the end of the SPI
transmission and remain valid until a different control word is transmitted or a power on
reset occurs. At each SPI transmission, the diagnosis bits as currently valid in the error
logic are transmitted. The behavior of the diagnosis bits is described in Section 2.5.
Table 1
Input Data Protocol
Bit
7
Status Register Reset: H = reset
6
OVLO: H = on, L = off
5
not used
4
MSB of 2bit chopper-OFF-time
3
LSB of 2bit chopper-OFF-time
2
PWM Operation mode: H = Fast decay, L = Slow decay
1
MSB of 2 bit chopper current limit
0
LSB of 2 bit chopper current limit TLE 6209 R
Data Sheet, Version 3.0
6
2001-10-15
Table 2
Programmable Chopper Current Limit
I
L_xx
Bit 1
Bit 0
Current limit
0
0
I
L_00
0
1
I
L_01
1
0
I
L_10
1
1
I
L_11
Note: For actual values, see page 16
Table 3
Programmable Chopper OFF-time
t
OFF_xx
Bit 4
Bit 3
Chopper-OFF-time
0
0
t
OFF_00
0
1
t
OFF_01
1
0
t
OFF_10
1
1
t
OFF_11
Note: For actual values, see page 16
Table 4
Diagnosis Data Protocol
Bit
H = Error/L = no error
7
Power supply fail
6
not used, always H
5
Short to
V
S
or across the load
4
Short to GND
3
Open load
2
MSB of Temperature Monitoring
1
LSB of Temperature Monitoring
0
Error-Flag
Table 5
Temperature Monitoring
Bit 2
Bit 1
Chip Temperature
0
0
Below Prewarning
0
1
Temperature Prewarning TLE 6209 R
Data Sheet, Version 3.0
7
2001-10-15
2.2
Supply
2.2.1
Logic Supply Voltage, Power-On-Reset
The logic is supplied with 5 V by the
V
CC
pin, separated from the power stage supply
V
S
.
The advantage of this system is that information stored in the logic remains intact even
in the event of failures in the supply voltage
V
S
. The power supply failure information can
be read out via the SPI. If
V
CC
falls below typically 4.5 V, the logic is shut down, all
internally stored data is deleted and the Output Stages are switched to tristate. The IC is
restarted on rising
V
CC
with a hysteresis of typically 80 mV
After this restart at increasing
V
CC
, or if the device is activated after having been set into
inhibit mode (INH L to H), the IC is initialized by Power-On-Reset (POR). After POR, all
SPI control bits are set to L. This setting remains valid until first SPI communication. Also
the error bits are reset by POR.
2.2.2
Power Supply Voltage
The power stages are connected to the supply voltage
V
S
. This voltage is monitored by
over voltage (OV) and under voltage (UV) comparators as described in Section 2.5.6.
The power supply voltage needs a blocking capacitor to GND.
2.3
Direct Inputs
2.3.1
Inhibit (sleep mode)
The INH input can be used to cut off the complete IC. By pulling the INH input t