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Intelligent Stepper Motor Driver ATA6830
1
Features 2-Phase 1 A Stepping Motor Driver Compensated Half Step Operation Chopper Current Control Unidirectional Single Wire Bus Interface with Error Feedback Intelligent Travel Operation Control Referencing by Extending or Retracting
Application Dynamic Headlamp Adjustment
Benefits Error Recognition with Feedback Short Circuit Protected Outputs Overtemperature Warning and Shut Off Supply Voltage Supervision
Electrostatic sensitive device.
Observe precautions for handling.
Description
The circuit serves to control a stepping motor for dynamic headlamp beam adjustment
in automobiles. Two chopper-controlled H-bridges serve as the stepping motor driver.
The circuit receives the commands to control the stepping motor by means of a unidi-
rectional serial single-wire bus.
An integrated process control independently moves the stepping motor into the new
desired position. This allows it to be automatically accelerated and slowed down. The
stepping motor is operated in compensated half-step operation. The maximum clock
frequency at which the stepping motor is operated depends on the supply voltage, the
chip temperature, the operating mode, and position difference.
Intelligent
Stepper Motor
Driver
ATA6830
Rev. 4575BBCD01/03 2
ATA6830
4575BBCD01/03
Figure 1. Block Diagram
Pin Configuration
Figure 2. Pinning HP-VFQFP-N28
SRB
SM1B
VBAT1B
SM2B
VBAT2B
SRA
SM1A
VBAT1A
SM2A
VBAT2A
D
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iv
e
r
Log
ic
C
r
u
i
si
n
g
Se
rvi
ce

C
o
n
t
ro
l
D
r
iv
e
r
Log
ic
UART
Command Interpreter
Test Logic
BUS
Voltage
Regulator
VSS
VDD
Bi
a
s
i
n
g
R
SET
O
s
c
i
ll
at
or
CO
S
T
e
m
p
er
a
t
u
r
e M
o
ni
t
o
r
S
u
pp
ly
M
o
ni
t
o
r
AG
N
D
ATA6830
MLP 7x7mm
0.8mm pitch
28 lead
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
ATA6830
VBAT1B
n.c.
SM1B
SRB
SM2B
n.c.
VBAT2B
n.
c
.
CO
S
RS
E
T
AG
N
D
VS
S
VD
D
BU
S
n.c
.
SC
I1
SC
O1
SC
I2
SC
O2
TA
TTE
MP
VBAT1A
n.c.
SM1A
SRA
SM2A
n.c.
VBAT2A 3
ATA6830
4575BBCD01/03
Pin Description
Pin
Symbol
Function
1
VBAT1A
Battery voltage
2
n.c.
Not connected
3
SM1A
Connection for stepping motor winding A
4
SRA
Sense resistor A connection
5
SM2A
Connection for stepping motor winding A
6
n.c.
Not connected
7
VBAT2A
Battery voltage
8
n.c.
Not connected
9
SCI1
Test pin, please connect to ground for EMC reasons
10
SCO1
Test pin, please connect to ground for EMC reasons
11
SCI2
Test pin, please connect to ground for EMC reasons
12
SCO2
Test pin, please connect to ground for EMC reasons
13
TA
Test pin, please connect to ground for EMC reasons
14
TTEMP
Test pin, please connect to ground for EMC reasons
15
VBAT2B
Battery voltage
16
n.c.
Not connected
17
SM2B
Connection for stepping motor winding B
18
SRB
Sense resistor B connection
19
SM1B
Connection for stepping motor winding B
20
n.c.
Not connected
21
VBAT1B
Battery voltage
22
BUS
Receives the control instructions via the single wire bus from the controller
23
VDD
5 V supply voltage output
24
VSS
Digital signal ground
25
AGND
Analog signal ground
26
RSET
Reference current setting. Connected externally with a resistor to AGND. The value of the resistor
determines all internal current sources and sinks.
27
COS
Oscillator pin, connected externally with a capacitor to AGND. The value of the capacitance determines
the chopper frequency and the baud rate for data reception.
28
n.c.
Not connected 4
ATA6830
4575BBCD01/03
Functional Description
Analog Blocks
Figure 3. Analog Blocks
The circuit contains an integrated 5 V regulator to supply the internal logic and analog
circuit blocks. The regulator uses an adjusted bandgap as voltage reference. Also all
other parts that require an excellent voltage reference, such as the voltage monitoring
block refer to the bandgap.
The bias generator derives its accurate currents from an external reference resistor. The
oscillator is used for clocking the digital system. All timings like the baud rate, the step
duration and the chopper frequency are determined from it. An external capacitor is
used for generating the frequency.
The voltage monitoring enables the circuit to drive the stepping motor at different battery
voltage levels. According to the battery voltage the stepping motor will be accelerated to
a maximum step velocity. In case of under or over voltage the motor will shut off. A tem-
perature monitoring is used for shut off at overtemperature conditions and current boost
in case of low temperature.
Oscillator
Bias
Generator
Bandgap
Voltage
Regulator
Voltage
Supervisor
COS
RSET
AGND
VSS
VDD
VBAT
Temperature
Supervisor
Bias
Clock
Supply
Reset
Voltage Levels
Temperature Levels 5
ATA6830
4575BBCD01/03
Digital Blocks
Figure 4. Digital Blocks
Figure 4 shows all digital blocks of the circuit. The stepping motor will be controlled by
commands via the bus input pin. An analog comparator is used as a level shifter at the
input. There is also a possibility of clamping the bus pin to ground. This will be used after
detecting an error to feedback this to the microcontroller.
The next block is a UART. Its task is clock recovery and data recognition of the incoming
bit stream. For clock recovery a special bitstream is used after each power on. The gen-
erated bitstream will be analyzed and after a correct parity check interpreted for
execution.
A sophisticated cruise control generates all control signals for the two H-bridge drivers.
It uses an internal step-time table for accelerating and decelerating the stepping motor
depending on the actual and desired position and the temperature and voltage levels.
Exception handling is integrated to interpret and react on the temperature, supply volt-
age, and coil-current signals from the analog part.
UART
Clock
Recovery
Bitstream
Recovery
Data
Recognition
&
Parity-Check
bitstream
rxd
shiftclk
BUS
VREF
reference run
new position
Step Time Memory
Maximum Step Time
New Step Time
Clk
Voltage Levels
Actual Step Time
Cruise Control
Desired Position
Instantaneous Position
Stepper Motor Control
Error Timer
Error Signals
Temperature Signals
Error Signals
Reset 6
ATA6830
4575BBCD01/03
Stepping Motor Driver
Figure 5. Stepping Motor Driver
Figure 5 shows the diagram of one H-bridge driver stage. It consists of two NMOS and
two PMOS power transistors. An external shunt is used for measuring the current flow-
ing through the motor coil. Additional comparators and current sensing circuitry is
integrated for error detection.
Data Communication
The circuit receives all commands for the stepping motor via a single wire bus. In idle
mode the bus pin is pulled up by an internal current source near to VBAT voltage. Dur-
ing the transmission the external transmitter has to pull down the bus level to send
information about data and clock timing. The used baud rate has to be about 2400 baud.
Because of oscillator tolerances a synchronization sequence has to be sent at the
beginning of data transfer.
Figure 6 shows the pattern used for this sequence. The circuit uses the 1-0-1-0
sequences for adjusting the internal bit time. Later on during data transfer every 1-0-1-0
sequence coming up randomly is used for resynchronization. Thus all tolerances that
occur during operation will be eliminated.
To obtain a synchronization of up to 15% oscillator tolerance the pattern has to be sent
at least 4 times.
Shunt
VBAT
SM1x
SM2x
SRx
Vref
Stepper Motor Control
Temperature
Warning
Temperature
Shutdown
Clk
Reset
Error Signals
Driver Logic
Temp. Shutdown
Temp. Warning 7
ATA6830
4575BBCD01/03
Figure 6. Synchronization Sequence
Between two commands a pause has to be included. This is necessary for a clear rec-
ogition of a new message frame (command). Figure 7 shows the timing diagram of two
commands.
Figure 7. Message Frame and Space
Every command consists of 16 bits. They will be sent with two bytes. Figure 8 shows the
message frame. The high byte is sent first, immediately followed by the low byte. Every
byte starts with a start bit and ends with a parity bit and a stop bit. The first start bit (level
0) after a pause (level 1) indicates the beginning of a new message frame. The value of
the parity bit has to be odd, i.e., the crossfooting of the byte including the parity bit is
odd. If a data packet is not recognized due to a transmission error (parity error), the
entire command is rejected.
Figure 8. Command Bits
START
BIT
STOP
BIT
PARITY
BIT
PARITY
BIT
STOP
BIT
START
BIT