Protection Array for ESD and
Over-Voltage Protection

The SP720 is an array of SCR/Diode bipolar structures for
ESD and over-voltage protection to sensitive input circuits.
The SP720 has 2 protection SCR/Diode device structures
per input. A total of 14 available inputs can be used to
protect up to 14 external signal or bus lines. Over-voltage
protection is from the IN (pins 1-7 and 9-15) to V+ or V-. The
SCR structures are designed for fast triggering at a
threshold of one +V

BE

diode threshold above V+ (Pin 16) or
a -V

BE

diode threshold below V- (Pin 8). From an IN input, a
clamp to V+ is activated if a transient pulse causes the input
to be increased to a voltage level greater than one V

BE


above V+. A similar clamp to V- is activated if a negative
pulse, one V

BE

less than V-, is applied to an IN input.
Standard ESD Human Body Model (HBM) Capability is:
Refer to Figure 1 and Table 1 for further detail. Refer to
Application Note AN9304 and AN9612 for additional
information.

Pinout

SP720 (PDIP, SOIC)

TOP VIEW

Features

ESD Interface Capability for HBM Standards
- MIL STD 3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 15kV
- IEC 1000-4-2, Direct Discharge,
Single Input. . . . . . . . . . . . . . . . . . . . . . . . 4kV (Level 2)
Two Inputs in Parallel . . . . . . . . . . . . . . . . 8kV (Level 4)
- IEC 1000-4-2, Air Discharge. . . . . . . . . . 15kV (Level 4)
High Peak Current Capability
- IEC 1000-4-5 (8/20

µ

s) . . . . . . . . . . . . . . . . . . . . . .

±

3A
- Single Pulse, 100

µ

s Pulse Width . . . . . . . . . . . . . .

±

2A
- Single Pulse, 4

µ

s Pulse Width . . . . . . . . . . . . . . . .

±

5A
Designed to Provide Over-Voltage Protection
- Single-Ended Voltage Range to . . . . . . . . . . . . . . .+30V
- Differential Voltage Range to . . . . . . . . . . . . . . . .

±

15V
Fast Switching . . . . . . . . . . . . . . . . . . . . . . . 2ns Risetime
Low Input Leakages . . . . . . . . . . . . . . . 1nA at 25

o

C (Typ)
Low Input Capacitance. . . . . . . . . . . . . . . . . . . . 3pF (Typ)
An Array of 14 SCR/Diode Pairs
Operating Temperature Range . . . . . . . . . -40

o

C to 105

o

C

Applications

Microprocessor/Logic Input Protection
Data Bus Protection
Analog Device Input Protection
Voltage Clamp

Functional Block Diagram

HBM STANDARD
MODE
R
C
ESD (V)

IEC 1000-4-2
Air
330

150pF
>15kV
Direct
330

150pF
>4kV
Direct, Dual Pins
330

150pF
>8kV
MIL-STD-3015.7
Direct, In-circuit
1.5k

100pF
>15kV

Ordering Information

PART NO.
TEMP. RANGE
(

o

C)
PACKAGE
PKG.
NO.

SP720AP
-40 to 105
16 Ld PDIP
E16.3
SP720AB
-40 to 105
16 Ld SOIC
M16.15
SP720ABT
-40 to 105
16 Ld SOIC
Tape and Reel
M16.15
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN
IN
IN
IN
IN
IN
V-
IN
V+
IN
IN
IN
IN
IN
IN
IN
V+ 16
1
8
2
3 - 7
9 - 15
IN
IN
IN
V-

Data Sheet
January 1998

[ /Title
(SP720
)
/Sub-
ject
(Elec-
tronic
Protec-
tion
Array
for
ESD
and
Over-
Volt-
age
Protec-
tion)
/Autho
r ()
/Key-
words
(TVS,
Tran-
sient
Sup-
pres-
sion,
Protec-
tion,
ESD,
IEC,
EMC,
Elec-
tro-
magnet
ic
Com-
6-4

ESD Capability

ESD capability is dependent on the application and dened
test standard. The evaluation results for various test
standards and methods based on Figure 1 are shown in
Table 1.
For the Modified MIL-STD-3015.7 condition that is defined
as an in-circuit method of ESD testing, the V+ and V- pins
have a return path to ground and the SP720 ESD capability
is typically greater than 15kV from 100pF through 1.5k

. By
strict definition of MIL-STD-3015.7 using pin-to-pin device
testing, the ESD voltage capability is greater than 6kV. The
MIL-STD-3015.7 results were determined from AT&T ESD
Test Lab measurements.
The HBM capability to the IEC 1000-4-2 standard is greater
than 15kV for air discharge (Level 4) and greater than 4kV
for direct discharge (Level 2). Dual pin capability (2 adjacent
pins in parallel) is well in excess of 8kV (Level 4).
For ESD testing of the SP720 to EIAJ IC121 Machine Model
(MM) standard, the results are typically better than 1kV from
200pF with no series resistance.

Absolute Maximum Ratings
Thermal Information

Continuous Supply Voltage, (V+) - (V-) . . . . . . . . . . . . . . . . . . +35V
Forward Peak Current, I

IN


to V

CC

, I

IN

to GND
(Refer to Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . .

±

2A, 100

µ

s
ESD Ratings and Capability (Figure 1, Table 1)
Load Dump and Reverse Battery (Note 2)
Thermal Resistance (Typical, Note 1) . . . . . . . . . . . . .

JA

(

o

C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
Maximum Storage Temperature Range . . . . . . . . . . -65

o

C to 150

o

C
Maximum Junction Temperature (Plastic Package) . . . . . . . . .150

o

C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

o

C
(SOIC Lead Tips Only)

CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specication is not implied.

NOTE:
1.

JA

is measured with the component mounted on an evaluation PC board in free air.

Electrical Specications


T

A

= -40

o

C to 105

o

C; V

IN

= 0.5V

CC

, Unless Otherwise Specied

PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS

Operating Voltage Range,
V

SUPPLY

= [(V+) - (V-)]
V

SUPPLY

-
2 to 30
-
V
Forward Voltage Drop:
IN to V-
IN to V+
V

FWDL

V

FWDH

I

IN

= 1A (Peak Pulse)
-
-
2
2
-
-
V
V
Input Leakage Current
I

IN

-20
5
20
nA
Quiescent Supply Current
I

QUIESCENT

-
50
200
nA
Equivalent SCR ON Threshold
Note 3
-
1.1
-
V
Equivalent SCR ON Resistance
V

FWD

/I

FWD

; Note 3
-
1
-

Input Capacitance
C

IN

-
3
-
pF
Input Switching Speed
t

ON

-
2
-
ns
NOTES:
2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the
V+ and V- pins are connected to the same supply voltage source as the device or control line under protection, a current limiting resistor should
be connected in series between the external supply and the SP720 supply pins to limit reverse battery current to within the rated maximum
limits. Bypass capacitors of typically 0.01

µ

F or larger from the V+ and V- pins to ground are recommended.
3. Refer to the Figure 3 graph for definitions of equivalent SCR ON Threshold and SCR ON Resistance. These characteristics are given here
for thumb-rule information to determine peak current and dissipation under EOS conditions.

TABLE 1. ESD TEST CONDITIONS
STANDARD
TYPE/MODE
R

D

C

D

±

V

D

MIL STD 3015.7 Modified HBM
1.5k

100pF 15kV
Standard HBM
1.5k

100pF
6kV
IEC 1000-4-2
HBM, Air Discharge
330

150pF 15kV
HBM, Direct Discharge
330

150pF
4kV
HBM, Direct Discharge,
Two Parallel Input Pins
330

150pF
8kV
EIAJ IC121
Machine Model
0k

200pF
1kV
H.V.
SUPPLY
°
±V
D
IN
DUT
C
D
R
1
IEC 1000-4-2: R
1
50 to 100M R
D
CHARGE
SWITCH
DISCHARGE
SWITCH
MIL STD 3015.7: R
1
1 to 10M

FIGURE 1. ELECTROSTATIC DISCHARGE TEST

SP720
6-5

FIGURE 2. LOW CURRENT SCR FORWARD VOLTAGE DROP
CURVE
FIGURE 3. HIGH CURRENT SCR FORWARD VOLTAGE DROP
CURVE
FIGURE 4. TYPICAL APPLICATION OF THE SP720 AS AN INPUT CLAMP FOR OVER-VOLTAGE, GREATER THAN 1V

BE

ABOVE V+ OR
LESS THAN -1V

BE

BELOW V-
600
800
1000
1200
FORWARD SCR VOLTAGE DROP (mV)
100
80
60
40
20
0
FOR
W
ARD SCR CURRENT (mA)
T
A
= 25
o
C
SINGLE PULSE
2.5
2
1.5
1
0.5
0
FOR
W
ARD SCR CURRENT (A)
T
A
= 25
o
C
SINGLE PULSE
V
FWD
I
FWD
0
1
2
3
FORWARD SCR VOLTAGE DROP (V)
EQUIV. SAT. ON
THRESHOLD ~ 1.1V
+V
CC
+V
CC
INPUT
DRIVERS
PROTECTION CIRCUIT
(1 OF 14 ON CHIP)
SP720 INPUT
OR
SIGNAL
SOURCES
IN 9-15
IN 1-7
SP720
V-
TO +V
CC
LINEAR OR
DIGITAL IC
INTERFACE
V+

SP720
6-6

Peak Transient Current Capability of the SP720

The peak transient current capability rises sharply as the
width of the current pulse narrows. Destructive testing was
done to fully evaluate the SP720s ability to withstand a wide
range of transient current pulses. The circuit used to
generate current pulses is shown in Figure 5.
The test circuit of Figure 5 is shown with a positive pulse
input. For a negative pulse input, the (-) current pulse input
goes to an SP720 IN input pin and the (+) current pulse
input goes to the SP720 V- pin. The V+ to V- supply of the
SP720 must be allowed to oat. (i.e., It is not tied to the
ground reference of the current pulse generator.) Figure 6
shows the point of overstress as dened by increased
leakage in excess of the data sheet published limits.
The maximum peak input current capability is dependent on
the V+ to V- voltage supply level, improving as the supply
voltage is reduced. Values of 0, 5, 15 and 30 voltages are
shown. The safe operating range of the transient peak
current should be limited to no more than 75% of the
measured overstress level for any given pulse width as
shown in Figure 6.
When adjacent input pins are paralleled, the sustained peak
current capability is increased to nearly twice that of a single
pin. For comparison, tests were run using dual pin
combinations 1+2, 3+4, 5+6, 7+9, 10+11, 12