of EE-Systems
University of Southern California
Los Angeles, CA
(213) 740-4458
pedram@ceng.usc.edu

ABSTRACT
High efficiency low voltage DC-DC conversion is a key enabler to
the design of power-efficient integrated circuits. Typically a star
configuration of the DC-DC converters, where only one converter
resides between the source and each load, is used to deliver
currents with appropriate voltage levels to different loads in the
circuit. In this paper we show that using a tree topology of suitably
chosen voltage regulators between the power source and loads
yields higher power efficiency in the power delivery network. We
formulize the problem of selecting the best set of regulators in a
tree topology as a dynamic program and efficiently solve it.
Experimental results demonstrate the efficacy of proposed problem
formulation and solution.
Categories and Subject Descriptors
B.8.2 [Performance and Reliability]: Performance Analysis and
Design Aides
General Terms
Algorithms, Design, Performance
Keywords
Low-power design, Power delivery network, DC-DC converter,
voltage regulator

1. INTRODUCTION
The International Technology Roadmap for Semiconductors
(ITRS) has projected an increase in the power consumption of
microprocessors for future technology nodes [1]. For example, for
complex designs done in 2007 with a feature size of 65nm and a
supply voltage of 1.1V, the power dissipation is 104 Watts. The
power delivery network (PDN) provides the power supply to the
processor. If improperly designed, this network can be a major
source of noise, such as ground bounce and IR drop [2].
The power delivery network is a critical design component in large
designs, especially for high-speed electronic systems [3]. A robust
PDN is required to achieve a high level of signal integrity. In
particular, PDN design comprises of three steps:
Establishing PDN target impedance,
Designing a proper system-level decoupling network,
Selecting the right voltage regulator modules.
A methodology for designing a good PDN is to define a target
impedance for the network that should be met over a broad
frequency band [4]. This parameter can be computed by assuming
a 5% allowable ripple in the voltage supply and a 50% switching
current in the rise and fall time of the processor clock. The target
impedance can then be calculated as:
I
V
I
V
Z
dd
dd
target
×
=
×
×
=
1
.
0
%
50
05
.
0

(1)
where V
dd
is the core voltage of the processor and I is the current
drawn by the microprocessor from the PDN. For the 65nm node,
I=104/1.1=94A and Z
target
=1.2m
. The decoupling capacitors play
an important role in the PDN as they act as charge reservoirs for
the switching circuits. The PDN target impedance has to be met
over a broad frequency band; low frequency, mid-frequency and
high frequency capacitors need to be suitably placed to meet this
requirement. It is difficult to provide sufficient decoupling in the
mid-frequency range of 200-300 MHz to 2-3 GHz. This presents a
challenge to designers if they are to meet the impedance
requirement over the entire frequency range [5]. This problem
however falls outside the scope of the present paper.

Every electronic circuit is designed to operate off of some supply
voltage, which is usually assumed to be constant. A voltage
regulator module (VRM) provides this substantially constant DC
output voltage regardless of changes in load current or input
voltage (this statement assumes that the load current and input
voltage are within the specified operating range for the part). A
switching power supply is a device transforming the voltage from
one level to another. Typically voltage is taken from the AC power
lines or unregulated DC power lines and transformed to the
regulated DC levels that logic circuits require. A switching-mode
power supply (SMPS) is a power supply that provides the power
supply function through low-loss components such as capacitors,
inductors, and transformers -- and the use of switches that are in
one of two states, ON or OFF. The advantage is that the switch
dissipates very little power in either of these two states and power
conversion can be accomplished with minimal power loss, which
equates to high efficiency. Usually a SMPS operates in a closed
loop system to regulate the power supply output, for example
through pulse-width modulation (PWM) or pulse-frequency
modulation (PFM).
Let the range of input voltages and load currents over which a
regulator can maintain a target voltage level within the specified
tolerance band (e.g., 5V with +/- 2% ripple) be specified. The


This research was sponsored in part by a grant from the National
Science Foundation.

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DAC 2007, June 48, 2007, San Diego, California, USA

Figure 1: The efficiency of TPS60503 as a function of input voltage and
output current [6].

regulators power efficiency may be calculated as the ratio of the
power that is delivered to the load to the power that is extracted
from the input source, i.e.,
in
in
out
out
I
V
I
V
=
(2)
Power efficiency is one of the most important figures of merit for a
voltage regulator and is a function of the input voltage and output
current of the VRM. Figure 1 shows the efficiency of a commercial
VRM as a function of input voltage and output current.
For DC-DC type conversion, there are many design choices. One
option is to use regulated charge-pump (switched capacitor) DC-
DC converter that utilize capacitors as energy storage elements.
They are often used when the load current demand is rather low (in
Amperes or less). Regulation is achieved by sensing the output
voltage through a resistor divider and modulating the charge pump
output current based on an error signal. The other option is to use a
regulated inductor-based (switched-mode) DC-DC converter,
which utilize inductors as energy storage elements. These
regulators are often used when the load current demand is high (in
tens or even hundreds of Amperes). Finally, one may use a linear
regulator (and its most efficient form a low-dropout regulator,
LDO), which operates by using a voltage-controlled current source
to force a fixed voltage to appear at the regulator output terminal.
The control circuitry must monitor (sense) the output voltage, and
adjust the current source (as required by the load) to hold the
output voltage at the desired value. The design limit of the current
source defines the maximum load current the regulator can source
and still maintain regulation. The dropout voltage of a linear
regulator is defined as the minimum voltage drop required across
the regulator to maintain output voltage regulation. The lower the
dropout voltage is, the higher the power efficiency of the linear
regulator is since the maximum power delivered to the load is
simply
(V
IN
V
dropout
)
×I
load
whereas the power extracted from the
input source is
V
IN
×(I
load
+I
quies
)
. Here,
I
quies
denotes the quiescent
current in the internal circuitry of the LDO. To have a high
efficiency LDO regulator, the dropout voltage and the quiescent
current must be minimized. In addition, the voltage difference
between input and output must be minimized since the internal
power dissipation of LDO regulators, which is
(V
OUT
V
IN
)
×I
load
,
accounts for the loss of power efficiency.
In recent years, PWM DC-DC converters integrated in standard
foundry-available digital CMOS processes have been
demonstrated. Although analog components, such as a bandgap
voltage reference, amplifiers, and oscillators,
are required to
implement the PWM and/or PFM control functions, power
dissipation due to digital logic is becoming increasingly important
to the overall power budget [7].
Each IC specifies its voltage regulator configuration in its
datasheets or comes with a companion document that defines the
power delivery feature set necessary to support that IC within a
larger electronic system. For example, the Intels VRM version
10.2 describes the Intel® processors' V
cc
power delivery
requirements for desktop computer systems using socket 478. This
includes design recommendations for DC-DC regulators which
convert the 12 V supply to the processor consumable V
cc
voltage
along with specific feature set implementation such as thermal
monitoring and Dynamic Voltage Identification.
In a large PCB design or equivalently in a complex SoC design,
there are many functional blocks (FBs) providing various
functionalities. Examples of processing elements are DSP or CPU
cores. Examples of other FBs are random logic or interface
blocks, MPEG encoder/decoder blocks, RF front-end, on-chip
memory, and various controllers. The V
cc
regulator design on a
specific platform (PCB or SoC) must meet the specifications of all
FBs supported in that platform.
Another low power design trend is emerging that makes the design
of the VRM tree
1
even more important. More precisely, multiple
voltage domains are being introduced on the same SoC in order to
meet a performance constraint while minimizing the overall power
dissipation of the syst