evious versions at the Internet Archive. Yahoo! is not affiliated with the authors of this page or responsible for its content.
LIN Bus Transceiver with Integrated Voltage Regulator ATA6623 ATA6625 Features Supply Voltage up to 40V Operating Voltage V
S
= 5V to 27V Typically 10 µA Supply Current During Sleep Mode Typically 57 µA Supply Current in Silent Mode Linear Low-drop Voltage Regulator:
Normal, Fail-safe, and Silent Mode
ATA6623: V
CC
= 3.3V ±2%
ATA6625: V
CC
= 5.0V ±2%
Sleep Mode: V
CC
is Switched Off V
CC
Undervoltage Detection with Reset Open Drain Output NRES (4 ms Reset Time) Voltage Regulator is Short-circuit and Over-temperature Protected LIN Physical Layer According to LIN Specification Revision 2.0 and SAEJ2602-2 Wake-up Capability via LIN Bus (90 µs Dominant) TXD Time-out Timer Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery Advanced EMC and ESD Performance ESD HBM 8 kV at Pins LIN and VS Following STM5.1 Interference and Damage Protection According to ISO/CD7637 Package: SO8
1.
Description
ATA6623/ATA6625 is a fully integrated LIN transceiver, designed according to the LIN
specification 2.0, with a low-drop voltage regulator (3.3V/5V/50 mA). The combination
of voltage regulator and bus transceiver makes it possible to develop simple, but pow-
erful, slave nodes in LIN Bus systems. ATA6623/ATA6625 is designed to handle the
low-speed data communication in vehicles (for example, in convenience electronics).
Improved slope control at the LIN driver ensures secure data communication up to
20 kBaud with an RC oscillator for the protocol handling. The bus output is designed
to withstand high voltage. Sleep Mode (voltage regulator switched off) and Silent
Mode (communication off; V
CC
voltage on) guarantee minimized current consumption.
LIN Bus
Transceiver
with Integrated
Voltage
Regulator
ATA6623
ATA6625
4957FAUTO02/08 2
4957FAUTO02/08
ATA6623/ATA6625
Figure 1-1.
Block Diagram
2.
Pin Configuration
Figure 2-1.
Pinning SO8
3
GND
2
EN
6
TXD
5
RXD
VCC
8
NRES
7
Short circuit and
overtemperature
protection
Normal/Silent/
Fail-safe Mode
3.3V/50 mA/2%
5V/50 mA/2%
Control
unit
Normal and
Fail-safe
Mode
RF-filter
LIN
VS
1
4
TXD
Time-out
timer
Slew rate control
Undervoltage reset
Sleep
mode
VCC
switched
off
Wake-up bus timer
ATA6623/25
Receiver
V
CC
-
+
V
CC
VCC
3
4
2
1
TXD
NRES
RXD
VS
8
7
6
5
GND
EN
LIN
Table 2-1.
Pin Description
Pin
Symbol
Function
1
VS
Battery supply
2
EN
Enables Normal Mode if the input is high
3
GND
Ground, heat sink
4
LIN
LIN bus line input/output
5
RXD
Receive data output
6
TXD
Transmit data input
7
NRES
Output undervoltage reset, low at reset
8
VCC
Output voltage regulator 3.3V/5V/50 mA 3
4957FAUTO02/08
ATA6623/ATA6625
3.
Functional Description
3.1
Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., LIN protocol layer), all
nodes with a LIN physical layer according to revision 2.0 can be mixed with LIN physical layer
nodes, which are according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3) without any
restrictions.
3.2
Supply Pin (VS)
LIN operating voltage is V
S
= 5V to 27V. An undervoltage detection is implemented to disable
transmission if V
S
falls below 5V, in order to avoid false bus messages. After switching on V
S
,
the IC starts with the Fail-safe Mode and the voltage regulator is switched on (i.e.,
3.3V/5V/50 mA).
The supply current in Sleep Mode is typically 10 µA and 57 µA in Silent Mode.
3.3
Ground Pin (GND)
The IC is neutral on the LIN pin in the event of GND disconnection. It is able to handle a ground
shift up to 11.5% of V
S
.
3.4
Voltage Regulator Output Pin (VCC)
The internal 3.3V/5V voltage regulator is capable of driving loads with up to 50 mA, supplying
the microcontroller and other ICs on the PCB and is protected against overload by means of cur-
rent limitation and overtemperature shut-down. Furthermore, the output voltage is monitored
and will cause a reset signal at the NRES output pin if it drops below a defined threshold V
thun
.
3.5
Undervoltage Reset Output (NRES)
If the V
CC
voltage falls below the undervoltage detection threshold of V
thun
, NRES switches to
low after tres_f (
Figure 6-1 on page 11
). Even if V
CC
= 0V the NRES stays low, because it is
internally driven from the V
S
voltage. If V
S
voltage ramps down, NRES stays low until V
S
< 1.5V
and then becomes highly resistant.
The implemented undervoltage delay keeps NRES low for t
Reset
= 4 ms after V
CC
reaches its
nominal value.
3.6
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown as well as an internal
pull-up resistor according to LIN specification 2.0 is implemented. The voltage range is from
27V to +40V. This pin exhibits no reverse current from the LIN bus to V
S
, even in the event of a
GND shift or V
Batt
disconnection. The LIN receiver thresholds are compatible with the LIN proto-
col specification.
The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are
slope controlled. 4
4957FAUTO02/08
ATA6623/ATA6625
3.7
Input Pin (TXD)
In Normal Mode the TXD pin is the microcontroller interface to control the state of the LIN output.
TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high or unconnected
(internal pull-up resistor), the LIN output transistor is turned off and the bus is in the recessive
state.
3.8
Dominant Time-out Function (TXD)
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being
driven permanently in the dominant state. If TXD is forced to low longer than t
DOM
> 6 ms, the
LIN bus driver is switched to the recessive state. Nevertheless, when switching to Sleep Mode,
the actual level at the TXD pin is relevant.
To reactivate the LIN bus driver, switch TXD to high (> 10 µs).
3.9
Output Pin (RXD)
The pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state) is
reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The
output has an internal pull-up structure with typically 5 k to V
CC
. The AC characteristics are
measured with an external load capacitor of 20 pF.
The output is short-circuit protected. In Unpowered Mode (that is, V
S
= 0V), RXD is switched off.
3.10
Enable Input Pin (EN)
This pin controls the Operation Mode of the interface. After power up of V
S
(battery), the IC
switches to Fail-safe Mode, even if EN is low or unconnected (internal pull-down resistor). If EN
is high, the interface is in Normal Mode.
A falling edge at EN while TXD is still high forces the device to Silent Mode. A falling edge at EN
while TXD is low forces the device to Sleep Mode. 5
4957FAUTO02/08
ATA6623/ATA6625
4.
Mode of Operation
Figure 4-1.
Mode of Operation
Unpowered Mode
V
Batt
= 0V
a: V
S
> 5V
b: V
S
< 4V
c: Bus wake-up event
d: NRES switches to low
Fail-safe Mode
Normal Mode
VCC: 3.3V/5V/50 mA
with undervoltage
monitoring
Communication: ON
VCC: 3.3V/5V/50 mA
with undervoltage monitoring
Communication: OFF
Silent Mode
VCC: 3.3V/5V/50 mA
with undervoltage monitoring
Communication: OFF
Sleep Mode
VCC: switched off
Communication: OFF
Go to silent command
a
TXD = 0
EN = 0
TXD = 1
EN = 0
EN = 1
EN = 1
EN = 1
b
b
b
c + d
d
c
b
Local wake-up event
Go to sleep command 6
4957FAUTO02/08
ATA6623/ATA6625
4.1
Normal Mode
This is the normal transmitting and Receiving Mode of the LIN Interface, in accordance with LIN
specification 2.0. The V
CC
voltage regulator operates with a 3.3V/5V output voltage, with a low
tolerance of ±2% and a maximum output current of 50 mA.
If an undervoltage condition occurs, NRES is switched to low and the IC changes its state to
Fail-safe Mode. All features are available.
4.2
Silent Mode
A falling edge at EN while TXD is high switches the IC into Silent Mode. The TXD Signal has to
be logic high during the Mode Select window (
Figure 4-2 on page 7
). The transmission path is
disabled in Silent Mode. The overall supply current from V
Batt
is a combination of the
I
VSsi
= 57 µA plus the V
CC
regulator output current I
VCCs
.
The 3.3V/5V regulator with 2% tolerance can source up to 50 mA. In Silent Mode the internal
slave termination between pin LIN and pin VS is disabled to minimize the power dissipation in
case pin LIN is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between pin
LIN and pin VS is present. The Silent Mode can be activated independently from the current
level on pin LIN.
If an undervoltage condition occurs, NRES is switched to low and the ATA6623/ATA6625
changes its state to Fail-safe Mode.
A voltage less than the LIN Pre-wake detection V
LINL
at pin LIN activates the internal LIN
receiver.
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time
period (t
bus
) and the following rising edge at pin LIN (see
Figure 4-3 on page 7
) results in a
remote wake-up request. The device switches from Silent Mode to Fail-safe Mode, then the
internal LIN slave termination resistor is switched on. The remote wake-up request is indicated
by a low level at pin RXD to interrupt the microcontroller (
Figure 4-3 on