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Voltage Regulator-Down (VRD) 10.0 Design Guide





Voltage Regulator-Down (VRD)
10.0

Design Guide
For Desktop Socket 478







February 2004


















Document Number:
252885-003
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VRD Design Guide



















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Pentium
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Copyright � 20032004, Intel Corporation



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Contents
1

Introduction.......................................................................................................................... 7

1.1

Terminology............................................................................................................ 8

2

Processor Voltage Requirements ..................................................................................... 11

2.1

Voltage and Current (REQUIRED) ....................................................................... 11

2.2

Loadline Definitions (REQUIRED)........................................................................ 11

2.3

TOB: Voltage Tolerance Band (REQUIRED) ....................................................... 20

2.3.1

Sources of Voltage Deviation and Input Parameters ............................ 20

2.3.2

TOB: Tolerance Band Calculation ........................................................ 21

2.3.2.1

Inductor RDC Current Sense TOB Calculations.................. 22

2.3.2.2

Resistor Current Sense TOB Calculations .......................... 22

2.3.2.3

FET RDS-ON Current Sense TOB Calculations ................. 23

2.4

VRD Thermal Compensation (REQUIRED) ........................................................ 23

2.5

Processor Electrical and Thermal Current Support (EXPECTED)....................... 24

2.6

Stability (EXPECTED) .......................................................................................... 24

2.7

Processor Power Sequencing (REQUIRED)........................................................ 24

2.8

Dynamic Voltage Identification (REQUIRED)...................................................... 25

2.8.1

Dynamic-Voltage Identification Functionality ........................................ 25

2.8.2

D-VID Validation.................................................................................... 27

2.8.3

Validation Summary.............................................................................. 28

2.9

Processor Vcc Overshoot (REQUIRED) ............................................................. 30

2.9.1

Specification Overview.......................................................................... 30

2.9.2

Example: Socket Vcc Overshoot Test .................................................. 34

2.10

Desktop VR Output Filter (REQUIRED) .............................................................. 35

2.11

Shutdown Response (REQUIRED) ...................................................................... 35

3

Control Inputs .................................................................................................................... 37

3.1

Output Enable (REQUIRED) ................................................................................ 37

3.2

Voltage Identification (VID [5:0]) (REQUIRED) .................................................... 37

3.3

Differential Remote Sense Input (REQUIRED) ................................................... 38

4

Input Voltage and Current ................................................................................................. 39

4.1

Input Voltages (EXPECTED)................................................................................ 39

4.2

Load Transient Effects on Input Current (EXPECTED)........................................ 39

5

Output Protection .............................................................................................................. 41

5.1

Over-Voltage Protection (OVP) (PROPOSED) ................................................... 41

5.2

Over-Current Protection (OCP) (PROPOSED) ................................................... 41

6

Output Indicators ............................................................................................................... 43

6.1

Processor Power Good Output (Vcc_PWRGD) (PROPOSED) ........................... 43

6.2

VRD Thermal Monitoring (PROPOSED) ............................................................. 43

6.3

Load Indicator Output (PROPOSED) .................................................................. 45

7

VccVID Voltage (PROPOSED) ......................................................................................... 47


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Motherboard Power Plane Recommendations (EXPECTED) .......................................... 49

8.1

Minimize Power Path DC Resistance................................................................... 49

8.2

Minimize Power Delivery Inductance.................................................................... 49

8.3

Four-Layer Boards................................................................................................ 49

8.4

Six-Layer Boards .................................................................................................. 50

Figures
Figure 1. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_A
Presented As a Deviation from VID.
Socket Loadline = 1.24 m
, VR Tolerance Band = �19 mV. .................................... 14

Figure 2. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_B
Presented As a Deviation from VID.
Socket Loadline = 1.30 m
, VR Tolerance Band = �25 mV. .................................... 15

Figure 3. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_C
Presented As a Deviation from VID.
Socket Loadline = 1.50 m
, VR Tolerance Band = �25 mV. .................................... 16

Figure 4. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_D
Presented As a Deviation From VID.
Socket Loadline = 1.50 m
, VR Tolerance Band = �19 mV. .................................... 17

Figure 5. Examples of High Volume Manufacturing Loadline Violations........................... 19

Figure 6. High Volume Manufacturing Compliant Loadline.............................................. 19

Figure 7. Power Sequence Block Diagram ....................................................................... 25

Figure 8. Power Sequence