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Assembling Nanoscale Circuits with Randomized Connections
Assembling Nanoscale Circuits with Randomized Connections
Tad Hogg, Yong Chen and Philip J. Kuekes September 8, 2005
Abstract
Molecular electronics is dicult to fabricate with precise positioning of large numbers of devices and
their connections. Self-assembly techniques can create such circuits but with some random variation
in their connection locations and characteristics. Using simulations, we show how to produce reliable
circuits in spite of this variation by adding enough redundant components to pass a sharp threshold in
likely circuit correctness. As an example of this approach, we examine a demultiplexer circuit, useful for
connecting nanoscale circuits with larger conventional circuits.
Keywords: molecular electronics, circuit reliability, nanotechnology, multiplexing, self-assembly
1
Introduction
Compared to microelectronics, nanoscale electronics is still in its infancy, as microelectronics was in the
1940s when the transistor was invented. The next major development in microelectronics was the integrated
circuit, in the 1950s, which ultimately facilitated interconnecting millions of microelectronic devices in an
economic, manufacturable, and scalable way for todays circuits. This interconnection technology, along with
decreasing device sizes, led to ultra-large integration of microelectronics for the information revolution as we
witness today. These circuits rely on the technological capability to precisely construct, place and connect
the components.
Molecular electronics holds the promise for signicantly denser circuits than is possible for current mi-
croelectronics. The research in nanoscale electronics has mainly focused on basic building blocks of the
nanoscale circuits: nanoscale dots and wires, switches and transistors that can turn an electric current on or
o as well as amplify signals. Examples include molecular switching devices [1], carbon nanotube transistors
and logic [2, 3], and single electron transistors with nanoscale crystals [4]. So far the progress has been
impressive. However, using these nanoscale devices for arithmetic or logic operations also requires intercon-
nection technology, i.e. methods to connect many devices into circuits. Although we know the functions we
need and the weakness of nanoscale devices that must be compensated for, we currently lack the technology
to reliably fabricate and connect large numbers of nanoscale devices into precise circuits. While lithography
can create microscale circuits with many components, high yield and low unit cost, this combination of
capabilities is not yet possible for molecular-scale devices.
Instead, creating a large number of molecular devices must rely on appropriately designed self-assembly
of the molecules. In principle, self-assembly can produce complex nanoscale structures as demonstrated
by biological processes. Unfortunately, our current physical and chemical self-assembly technology at the
nanoscale is limited to creating simple, regular or random structures. In either case, the assembled structures
have low information content. Self-assembly [5] can create a wide range of structures at many length scales.
For nanoscale circuits, the challenge is to design components simple enough to fabricate by self-assembly
that are nevertheless useful for constructing complex circuits. Arrays of parallel nanowires, microns long
with nanometer pitch, are one such example [6, 7]. Two of these arrays, placed orthogonally with molecules
between the crossed wires, can be congured to provide electronic memory and logic circuits [8, 9, 10, 11].
Conguring and using these circuits requires electrical connections to standard microelectronics so that
the nanowires are individually addressable [12, 13]. The most direct approach spreads the nanowires far The authors are at HP Labs, 1501 Page Mill Road, Palo Alto, CA.
to appear in IEEE Trans. on Nanotechnology
1 enough apart to be connected using conventional lithography, and has been used to create a functioning
demultiplexer [9]. However this greatly increases the area of the circuit, thereby negating the advantage of
nanoscale circuitry when applied to a large number of components.
A better approach, used by all existing memory chips, is the demultiplexer circuit, in which M = 2 log
2
N
external addressing wires can individually address N data wires. Since only the small number of address
wires need to connect to the micron scale, using demultiplexers with nanoscale circuits retains the density
advantages of the nanoelectronics. Unfortunately, demultiplexers require a complex pattern of connections,
which cant be fabricated at the nanoscale by current technology.
This paper presents a theoretical study of a technique to fabricate demultiplexers at the nanoscale us-
ing random self-assembly. We consider a regular self-assembly process to create an array of many parallel
nanowires. Ordinary micron-scale lithography makes the small number of micron-scale address wires. Con-
nections between these sets of wires are formed with two-way AND logic elements at their cross points.
These connections are formed by a feasible random physical process. This process only allows control over
the density of connections but not their precise location, thereby precluding the complex connection pattern
of a standard demultiplexer. Such random connections are much easier to fabricate than precisely specied
connections, e.g., by self-assembly methods. On the other hand, the randomness leads to many defects and
uncertainties in the circuits. In this paper, we use theoretical modeling to investigate this trade-o.
This work extends the range of nanoscale self-assembly techniques beyond the regular structures described
above for a conventional demultiplexer circuit. It thus points the way to developing complex nanoscale circuits
by combining regular and random structures. We show that in spite of the randomness, with a sucient
number of extra wires, the resulting circuit has a high probability to correctly function as a demultiplexer,
i.e., we can achieve high yield of correct circuits. The ability to fabricate nanoscale circuits with high
yield but without precise control of individual connections relies on the appearance of sharp thresholds
in yield as a function of the number of extra components included in the circuit. That is, instead of a
gradual improvement in yield with an increasing number of extra components, we see an abrupt change
from yields near zero to values near one at a specic threshold. This behavior, exhibited by our simulation
results, is a general property of many statistical systems, including physical systems [14, 15], mathematical
structures [16], biology [17], computation [18] and engineered systems such as wireless networks [19]. Such
thresholds in performance enable reliable operation by detecting and adjusting to faults so as to exceed the
threshold [8, 20, 21].
2
Demultiplexer Circuits
Electronic circuits often involve large numbers of devices but have limited space for external communication,
e.g., via a limited number of pins on an integrated circuit. Demultiplexer circuits are often used to solve this
problem by allowing a small number of wires to selectively address a larger number of data wires [22, 23].
For an example, Fig. 1 shows a demultiplexer circuit, in which six addressing wires (marked A, . . . , F )
address eight data wires (marked 1, . . . , 8). Each dot on an intersection between an addressing and data
wire represents a two-way AND logic element (as shown in the insert in Fig. 1). A crossing with no dot
indicates no connection between the wires. The two-way AND logic element can be a direct connection, a
diode, or a transistor between the two wires. Selecting the type of connecting device is a choice between
ease of fabrication and operation eciency. For instance, resistor connections are the easiest to fabricate but
suer from increased power use and lower discrimination between on and o states compared to more
complex devices.
As an application of this circuit, a single additional wire (not shown) connected to all the data wires at
the top of the circuit would set all data wires to 1 at the top. An address wire whose signal is zero will set
all its connected data wires to zero. Thus a data wire will only be set to 1 if the signals on all the addressing
wires it connects to are 1. The circuit could be used to introduce external signals to exactly one of the data
wires, e.g., as part of a write/read operation for a molecular memory.
With the pattern of connections shown in Fig. 1, the addressing wires group into pairs whose signals are
always complementary, i.e., either 0,1 or 1,0. These addressing signals are readily achieved by connecting
each pair to a single external communication wire, which branches into two addressing wires, presenting
both the original signal and its inverse. Presenting any set of binary values for the three communication
2 1 2 3 4 5 6 7 8
c
b
a
A
B
C
D
E
F
Figure 1: Demultiplexer circuit with 8 data wires (1, . . . , 8) and 6 addressing wires. The binary pattern
of connections shown here has valid addresses consisting of alternating 0s and 1s, which can be provided
externally by 3 wires (a, b, c), each connected to two addressing wires, one of which is via an inverter circuit.